ISPGDX160-5B272 Lattice Semiconductor, ISPGDX160-5B272 Datasheet
ISPGDX160-5B272
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ISPGDX160-5B272 Summary of contents
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... Simulator Netlist Generation for Easy Board-Level Simulation Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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... Lattice de- vices in hot swap environments can be downloaded from the Lattice web site at www.latticesemi.com. ispGDX DEVICE ispGDX80A ispGDX120A 1 100-Pin TQFP 176-Pin TQFP/ 160-Pin PQFP 2 ispGDX160/A 120 160 ...
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Architecture The ispGDX architecture is different from traditional PLD architectures, in keeping with its unique application fo- cus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are ...
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Applications The ispGDX family architecture has been developed to deliver an in-system programmable signal routing solu- tion with high speed and high flexibility. The devices are targeted for three similar but distinct classes of end- system applications: Programmable, Random Signal ...
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Applications (Cont.) Figure 3. Address Demultiplex/Data Buffering XCVR I/OA I/OB OEA OEB Address Latch D Q CLK Figure 4. Data Bus Byte Swapper XCVR D0-7 I/OA I/OB OEA OEB XCVR D8-15 I/OA I/OB OEA OEB Figure 5. Four-Port Memory Interface ...
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Absolute Maximum Ratings Supply Voltage V ................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A 160 Active High B ...
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External Timing Parameters TEST 1 PARAMETER # COND Data Propagation Delay from any I/O pin to any I/O pin t sel A 2 Data Propagation Delay from MUXsel Inputs to any Output f – 3 Clock ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 21 Input Buffer Delay io GRP t 22 GRP Delay grp MUX t 23 I/O Cell MUX A/B/C/D Data Delay muxd t 24 I/O Cell MUX A/B/C/D Data Select muxs Register t ...
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Switching Waveforms VALID INPUT MUXSEL (I/O INPUT) t sel DATA (I/O INPUT) VALID INPUT t pd COMBINATORIAL I/O OUTPUT Combinatorial Output OE (I/O INPUT) t dis COMBINATORIAL I/O OUTPUT I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ...
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Development System The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-to- use Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool ...
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... A sample file looks like this: //32-bit data exchange from A-bus to B-bus DESIGN a2bexch PART ispGDX160-5Q208; PARAM SECURITY ON; PARAM PULLUP OFF; SET busA [dataA0..dataA31]; SET busB [dataB0..dataB31]; BIDI busA {A0..A31} PULLUP SLOWSLEW; ...
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Download .jed - JEDEC Device Programming File Third-Party Timing Simulation The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. In-System ...
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... Each I/O register is structured as shown in Figure 7. The operation of the boundary scan test circuitry in the ispGDX160 is dependent on the fuse pattern programmed into the device. The boundary scan circuitry on the ispGDX160A, ispGDX120A and ispGDX80A operates independently of the programmed pattern. This allows customers using boundary scan test to have full test capability with only a single BSDL file ...
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... DEVICE 8-BIT ISP ID ispGDX80A 0111 0111 ispGDX120A 0111 1000 ispGDX160/A 0111 1001 Specifications ispGDX Family algorithm. The eight-bit device ID can be read from the device in Idle State for ISP device identification. Details of the programming sequence are transparent to the user and are handled by Lattice ISP Daisy Chain Downlowad (ispDCD), ispCODE ‘ ...
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... Output/Output Pin – Serial data output during ISP programming or Boundary Scan mode. GND Ground (GND) VCC Vcc – Supply voltage (5V Connect pins are not to be connected to any active signals, VCC or GND. Signal Locations: ispGDX160/A Signal TOE 178 RESET 185 Y0, Y1, Y2, Y3, 75, 76, 180, 181 BSCAN/ispEN 183 ...
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... I/O Locations: ispGDX160/A 208 272 Signal PQFP BGA Signal PQFP BGA I I/O A32 I I/O A33 I I/O A34 I I/O A35 I I/O A36 I I/O A37 I I/O A38 I I/O A39 I I I/O B1 I/O A10 13 G2 I/O B2 I/O A11 14 G1 I/O B3 I/O A12 16 H2 I/O B4 I/O A13 18 J4 I/O B5 I/O A14 19 J3 I/O B6 I/O A15 ...
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... Signal Configuration: ispGDX160/A ispGDX160/A 272-Ball BGA Signal Diagram I/O I/O I I/O I/O I D11 I/O I/O I/O I/O I C39 I/O I/O I/O D GND NC 1 VCC C36 C38 D0 I/O I C33 C37 I/O I/O I/O F C35 VCC C30 C32 I/O I/O I/O I/O G C28 C29 ...
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... Pin Configuration: ispGDX160/A ispGDX160/A 208-Pin PQFP (with Heat Spreader) Pinout Diagram Control Data 1 — VCC CLK I I MUXsel1 I MUXsel2 I — GND CLK I I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I ...
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Signal Locations: ispGDX120A Signal TOE 150 RESET 156 Y0, Y1, Y2, Y3, 63, 64, 152, 153 BSCAN/ispEN 154 TDI/SDI 69 TCK/SCLK 68 TMS/MODE 67 TDO/SDO 66 GND 8, 17, 27, 37, 50, 65, 77, 91, 101, 110, 120, 129, 144, ...
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Pin Configuration: ispGDX120A ispGDX120A 176-Pin TQFP Pinout Diagram Control Data 1 1 — NC — — VCC 4 CLK I I MUXsel1 I MUXsel2 I ...
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Pin Configuration: ispGDX120A ispGDX120A 160-Pin PQFP Pinout Diagram Control Data — VCC 1 2 CLK I I MUXsel1 I MUXsel2 I — GND 6 CLK 7 I/O A ...
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Signal Locations: ispGDX80A Signal 100-Pin TQFP Y1/TOE RESET 89 BSCAN/ispEN 35 TDI/SDI 39 TCK/SCLK 36 TMS/MODE 86 TDO/SDO 85 GND 6, 18, 29, 45, 56, 68, 79, 95 VCC 12, 37, 62, 88 I/O Locations: ispGDX80A Signal ...
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Pin Configuration: ispGDX80A ispGDX80A 100-Pin TQFP Pinout Diagram Control Data CLK I I MUXsel1 I MUXsel2 I CLK I GND 6 — ...
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... Specifications ispGDX Family – X XXXX X Grade Blank = Commercial Package Q208 = PQFP (with Heat Spreader) T176 = TQFP Q160 = PQFP B272 = BGA T100 = TQFP COMMERCIAL ORDERING NUMBER ispGDX160-5Q208* ispGDX160-5B272* ispGDX160-7Q208* ispGDX160-7B272* ispGDX160A-5Q208 ispGDX160A-5B272 ispGDX160A-7Q208 ispGDX160A-7B272 ispGDX120A-5T176 ispGDX120A-5Q160 ispGDX120A-7T176 ispGDX120A-7Q160 ispGDX80A-5T100 ispGDX80A-7T100 25 0212/ispGDX ...