ISPGDX LATTICE [Lattice Semiconductor], ISPGDX Datasheet
ISPGDX
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ISPGDX Summary of contents
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... Interrupts, DMAREQs, etc) • Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The ispGDX Family consists of three members with 80, 120 and 160 Programmable I/Os. These devices are available in packages ranging from the 100-pin TQFP to the 208-pin PQFP. The devices feature fast operation, with input-to-output signal delays (Tpd) of 5ns and clock- to-output delays of 5ns ...
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... Test Access Port via a special set of private com- mands or through Lattice’s industry-standard ISP protocol. The BSCAN/ispEN pin is used to make this selection. The ispGDX I/Os are designed to withstand “live inser- tion” system environments. The I/O buffers are disabled during power-up and power-down cycles. When design- 2 CMOS technology ...
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... Figure 1. The four data inputs to the MUX (called MUXA, MUXB, MUXC and MUXD) come from I/O signals found in the GRP. Each MUX data input can access one quarter of the total I/Os. For example 160 I/O ispGDX, each ® devices, there are data input can connect to one of 40 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2 ...
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... ISP/JTAG As a result, the ispGDX architecture has been defined to Interface support PSR and PRSI applications (including bidirec- tional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a minimal number of restrictions as described below ...
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... OEA OEB when the security cell is programmed. Security Bit The ispGDX Family includes a security bit feature that prevents reading the device program once set. Even when set, it does not inhibit reading the UES or device ID code. It can be erased only via a device bulk erase. ...
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... V 1 Input High Voltage IH 1. Typical 100mV of input hysteresis. o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER ispGDX Erase/Reprogram Cycles Specifications ispGDX Family 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0°C to +70°C A TYPICAL MINIMUM 10,000 6 MIN. MAX. UNITS 5.25 4.75 0 ...
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... One output at a time for a maximum duration of one second. V degradation. Characterized but not 100% tested. 2. Typical values are and MHz = (0.0114 x I/O cell fanout) + 0.06 CC e.g. An input driving four I/O cells at 40 MHz results in a dynamic I Specifications ispGDX Family GND to 3.0V ≤ 1.5ns 10% to 90% 1.5V Device 1.5V Output See figure at right * C L includes Test Fixture and Probe Capacitance ...
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... Output Skew (tgco1 across chip) 1. All timings measured with one output switching, fast output slew rate setting, except ispGDX timings are specified with a GRP load (fanout) of four I/O cells. The figure at right shows the Maximum ∆ GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK, MUXsel0-1) ...
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... Clock Delay, Y0/1/2/3 gy0/1/2/3 Global Reset t 45 Global Reset to I/O Register/Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX Family 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...
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... I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ispGDX Timing Model MUX0 MUX1 GRP tgrp #22 tcio #43 Clock Y0,1,2,3 tgy0/1/2/3 #44 Specifications ispGDX Family DATA (I/O INPUT) CLK REGISTERED I/O OUTPUT t en RESET REGISTERED I/O OUTPUT wl tgoe #41 tmuxd #23 tmuxs #24 tiobp #31 tmuxc #33, # tiolat #25 tiod #35, #36 ...
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... Solaris and HP-UX Versions Available In-System Programmability All necessary programming of the ispGDXV/VA is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. On-chip programming can be accomplished using an IEEE 1149 ...
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... The ispGDXV/VA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface. The boundary scan circuitry on the ispGDXV/VA Family operates independently of the programmed pattern. This allows customers using boundary scan test to have full test capability with only a single BSDL file. ...
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... U previous X cell Shift DR Figure 8. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 TCK TMS or TDI TDO tsu = 0.1µs (min.) Specifications ispGDX Family Normal Function Normal Function Update SCANOUT (to next cell) Clock Select-DR-Scan ...
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... VCC 1, 17, 33, 49, 65, 89, 105, 121, 137, 153, 170, 184 193 NC 1 73, 74, 156, 179 1. NC pins are not to be connected to any active signals, VCC or GND. Specifications ispGDX Family Description 208-Pin PQFP A12 D10 V10, Y10, C11, A11 B10 Y12 ...
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... M3 I/O B17 I/O A26 32 M4 I/O B18 I/O B19 I/O A27 34 N2 I/O A28 36 P1 I/O B20 I/O A29 37 P2 I/O B21 I/O A30 38 R1 I/O B22 I/O A31 39 P3 I/O B23 Specifications ispGDX Family 208 272 208 272 Signal PQFP BGA 40 R2 I/O B24 86 W13 41 T1 I/O B25 87 V13 42 P4 I/O B26 88 Y14 43 R3 I/O B27 90 ...
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... Signal Configuration: ispGDX160A ispGDX160A 272-Ball BGA Signal Diagram I/O I/O I I/O I/O I D11 I/O I/O I/O I/O I C39 I/O I/O I/O D GND NC 1 VCC C36 C38 D0 I/O I C33 C37 I/O I/O I/O F C35 VCC C30 C32 I/O I/O I/O I/O G C28 C29 ...
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... Pin Configuration: ispGDX160A ispGDX160A 208-Pin PQFP (with Heat Spreader) Pinout Diagram Control Data 1 — VCC CLK I I MUXsel1 I MUXsel2 I — GND CLK I I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I ...
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... I/O B14 I/O A21 29 27 I/O B15 I/O B16 I/O A22 30 28 I/O A23 31 29 I/O B17 Specifications ispGDX Family 176-Pin TQFP 136 142 57, 58, 138, 139 140 15, 25, 35, 44, 59, 71, 81, 91, 100, 110, 119, 130, 147, 156 1, 17, 33, 49, 73, 89, 105, 122, 141, 145 176 ...
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... Pin Configuration: ispGDX120A ispGDX120A 176-Pin TQFP Pinout Diagram Control Data 1 1 — NC — — VCC 4 CLK I I MUXsel1 I MUXsel2 I — GND 8 9 CLK I I MUXsel1 I MUXsel2 I CLK I I ...
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... Pin Configuration: ispGDX120A ispGDX120A 160-Pin PQFP Pinout Diagram Control Data — VCC 1 CLK I I MUXsel1 I MUXsel2 I — GND 6 CLK I I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I MUXsel2 I — ...
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... I/O A10 13 I/O A11 14 I/O B11 I/O A12 15 I/O B12 I/O A13 16 I/O B13 I/O A14 17 I/O B14 I/O B15 I/O A15 19 I/O A16 20 I/O B16 I/O A17 21 I/O B17 I/O A18 22 I/O B18 I/O B19 I/O A19 23 Specifications ispGDX Family 100 TQFP Signal 100 TQFP Signal I/O C8 ...
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... Pin Configuration: ispGDX80A ispGDX80A 100-Pin TQFP Pinout Diagram Control Data CLK I I MUXsel1 I MUXsel2 I CLK I GND 6 — MUXsel1 MUXsel2 I CLK I I — VCC 12 I/O A10 13 MUXsel1 I/O A11 14 MUXsel2 I/O A12 15 CLK OE I/O A13 16 MUXsel1 I/O A14 17 — ...
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... Tpd Ordering Information I/O PINS tpd (ns 160A 120 Specifications ispGDX Family – X XXXX X Grade Blank = Commercial Package Q208 = PQFP (with Heat Spreader) T176 = TQFP Q160 = PQFP B272 = BGA T100 = TQFP COMMERCIAL ORDERING NUMBER ispGDX160A-5Q208 ispGDX160A-5B272 ispGDX160A-7Q208 ispGDX160A-7B272 ...