TN1112 LATTICE [Lattice Semiconductor], TN1112 Datasheet

TN1112

Manufacturer Part Number

TN1112

Description

Input Hysteresis in Lattice CPLD and FPGA Devices

Manufacturer

LATTICE [Lattice Semiconductor]

Datasheet

1.TN1112.pdf (6 pages)

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September 2006

Introduction

In order to optimize speed in Lattice devices such as the ispMACH™ 4000 and MachXO™, device inputs are con-

ﬁgurable with internal pull-up, pull-down, bus-hold latch or no bus maintenance. Typically, inputs can tolerate rise

and fall times in the 50ns to 100ns range. When interfacing to slow input signals with input rise and fall time in hun-

dreds of nanoseconds, external board design techniques are necessary to make the slow input signals immune to

input noise that may be injected. This technical note suggests a few such techniques.

Input Circuit Techniques

Simple external circuitry along with the internal bus maintenance circuit can signiﬁcantly improve slow rising and

falling input noise immunity. Three common methods are described below.

Figure 1. Method 1: Input Series Resistor

Figure 2. Method 2: Input and Feedback Resistor

Figure 3. Method 3: Input Resistor and Feedback Capacitor

The following experimental data was collected to demonstrate the improvement that can be achieved with the dif-

ferent methods as compared to inputs without any external circuitry. The tables below highlight the maximum input

rise (t

Test Device:

I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on

Temperature: Room temperature

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

RISE

) and fall (t

External Input Circuit

MachXO

Method 1

None

FALL

) time of the results.

Input Series Resistor

HCout

Cin

Input Hysteresis in Lattice CPLD and

100 Ω

470 Ω

680 Ω

—

>15ms

<54ns

500ns

65ns

RISE

FPGA Devices

>15ms

<56ns

470ns

63ns

FALL

Technical Note TN1112

Cout

tn1112_01.1

Related parts for TN1112

TN1112 Summary of contents

Page 1

... The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com Input Hysteresis in Lattice CPLD and Cin 20 HCout 21 Cin 20 HCout 21 Cin 20 Input Series Resistor t RISE — <54ns 100 Ω 65ns 470 Ω 500ns 680 Ω >15ms 1 FPGA Devices Technical Note TN1112 59 Cout 59 Cout 59 Cout t FALL <56ns 63ns 470ns >15ms tn1112_01.1 ...

Page 2

Lattice Semiconductor Test Device: ispMACH 4128V I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on Temperature: Room temperature External Input Input Series Circuit Resistor None 100 Ω Method 1 4.7K Ω 100 Ω Method 2 100 Ω Method 3 ...

Page 3

Lattice Semiconductor Figure 5. Input Measured at Point A Figure 6. Zoomed View of Rising Edge of Figure 5 Lattice CPLD and FPGA Devices 3 Input Hysteresis in ...

Page 4

Lattice Semiconductor Input Hysteresis Figure 7 demonstrates the input signal with slow ramp rate virtually follow the ramp rate of MachXO output. Figure 7. Input measured at Point B Note “jump” at transition point. Figure 8. Zoomed View of Rising ...

Page 5

Lattice Semiconductor With a fast slew rate input, the signal will stay around the threshold region for a short time. With a slower signal, which stays in the threshold region for a long time, the noise will have more time ...

Page 6

Lattice Semiconductor Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date April 2006 September 2006 Version 01.0 Initial release. 01.1 Waveforms updated. Detailed explanation added. 6 Input Hysteresis in Lattice CPLD ...

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