GAL6001B-30LP Lattice Semiconductor Corp., GAL6001B-30LP Datasheet

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GAL6001B-30LP

Manufacturer Part Number
GAL6001B-30LP
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Manufacturer:
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Quantity:
20 000
• HIGH PERFORMANCE E
• LOW POWER CMOS
• E
• UNPRECEDENTED FUNCTIONAL DENSITY
• HIGH-LEVEL DESIGN FLEXIBILITY
• APPLICATIONS INCLUDE:
Using a high performance E
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24-
pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time,
coupled with E
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6001_02
Features
Description
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
— 90mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
2
CELL TECHNOLOGY
and FPLA Devices
2
CMOS reprogrammable cells, enable 100% AC, DC,
®
Advanced CMOS Technology
2
CMOS
2
CMOS technology, Lattice
®
TECHNOLOGY
®
1
Functional Block Diagram
Macrocell Names
Pin Names
Pin Configuration
ILMC
IOLMC I/O LOGIC MACROCELL
BLMC
OLMC
I
ICLK
OCLK
0
NC
- I
INPUTS
2-11
I
I
I
I
I
I
CLOCK
INPUT
10
11
5
7
9
{
12
4
INPUT LOGIC MACROCELL
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
INPUT
INPUT CLOCK
OUTPUT CLOCK
GAL6001
Top View
2
11
14
2
ILMC
PLCC
0
7
BLMC
High Performance E
28
ICLK
16
D
E
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
AND
OR
Generic Array Logic™
I/O/Q
V
GND
CC
GAL6001
D
E
OUTPUT
ENABLE
I/ICLK
14
GND
BIDIRECTIONAL
POWER (+5)
GROUND
23
OLMC
I
I
I
I
I
I
I
I
I
I
OCLK
2
1
6
12
CMOS FPLA
6001
14
DIP
GAL
23
IOLMC
July 1997
18
24
13
{
OUTPUTS
OUTPUT
14 - 23
CLOCK
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK

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GAL6001B-30LP Summary of contents

Page 1

... Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 2

... GAL6001 Ordering Information Commercial Grade Specifications Part Number Description GAL6001B Device Name Speed (ns Low Power Power XXXXXXXX Specifications GAL6001 Grade Blank = Commercial Package P = Plastic DIP J = PLCC ...

Page 3

Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC) The GAL6001 features two configurable input sections. The ILMC section corresponds to the dedicated input pins (2-11) and the IOLMC to the I/O pins (14-23). Each input section is configurable as ...

Page 4

ILMC and IOLMC Configurations ICLK 10 INPUT or I/O ILMC (Input Logic Macrocell) JEDEC Fuse Numbers ISYN 8218 LATCH INVALID 0 REG LATCH ILMC/IOLMC Generic Logic Block Diagram IOLMC (I/O Logic Macrocell) ...

Page 5

OLMC and BLMC Configurations OLMC ONLY XORD(i) D XORE(i) E CKS(i) OLMC (Output Logic Macrocell) JEDEC Fuse Numbers OLMC OCLK OSYN 0 8178 8179 1 8182 8183 2 8186 8187 3 8190 8191 4 8194 8195 5 8198 8199 6 ...

Page 6

GAL6001 Logic Diagram LTC H. Specifications GAL6001 LTCH EG. 6 REG. MUX ...

Page 7

GAL6001 Logic Diagram (Continued) The number of Differential Product Terms that may switch is limited to a maximum of 15. Refer to the Differential Product Term Switching Applications sec- tion of this data sheet for a full explanation. Specifications GAL6001 ...

Page 8

Absolute Maximum Ratings Supply voltage V ...................................... –0.5 to +7V CC Input voltage applied .......................... –2 Off-state output voltage applied ......... –2 Storage Temperature ................................ –65 to 150 C Ambient Temperature with Power Applied ........................................ –55 ...

Page 9

AC Switching Characteristics TEST DESCRIPTION PARAMETER 1 COND . t pd1 A Combinatorial Input to Combinatorial Output t pd2 A Feedback or I/O to Combinatorial Output t pd3 A Transparent Latch Input to Combinatorial Output t co1 A Input Latch ...

Page 10

Switching Waveforms INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT Combinatorial Output INPUT or VALID INPUT I/O FEEDBACK t t su1 h1 ICLK (LATCH) t pd3 COMBINATORIAL OUTPUT Latched Input INPUT or VALID INPUT I/O FEEDBACK t su4 Sum Term CLK REGISTERED ...

Page 11

Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY f max with No Feedback Note: fmax with no feedback ...

Page 12

Array Description 2 The GAL6001 contains two E reprogrammable arrays. The first is an AND array and the second array. These arrays are described in detail below. AND ARRAY The AND array is organized as 78 inputs ...

Page 13

Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL6001 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr ...

Page 14

Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 ...

Page 15

Typical AC and DC Characteristic Diagrams Vol vs Iol 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta Icc ...

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