IRF9530STRLPBF Vishay, IRF9530STRLPBF Datasheet - Page 7

• Manufacturer Part Number: IRF9530STRLPBF
• Description: MOSFET P-CH 100V 12A D2PAK
• Manufacturer: Vishay

Specifications of IRF9530STRLPBF

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 300 mOhm @ 7.2A, 10V
• Drain To Source Voltage (vdss): 100V
• Current - Continuous Drain (id) @ 25° C: 12A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 38nC @ 10V
• Input Capacitance (ciss) @ Vds: 860pF @ 25V
• Power - Max: 3.7W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Transistor Polarity: P Channel
• Continuous Drain Current Id: -12A
• Drain Source Voltage Vds: -100V
• On Resistance Rds(on): 300mohm
• Rds(on) Test Voltage Vgs: -10V
• Leaded Process Compatible: Yes
• Configuration: Single
• Resistance Drain-source Rds (on): 0.3 Ohms
• Drain-source Breakdown Voltage: - 100 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 12 A
• Power Dissipation: 3.7 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91077.
Document Number: 91077
S10-1728-Rev. B, 02-Aug-10
Re-applied
voltage
Reverse
recovery
current
+
R
-
g
D.U.T.
• Compliment N-Channel of D.U.T. for driver
Note
a. V
Note
D.U.T. V
Driver gate drive
D.U.T. l
Inductor current
GS
= - 5 V for logic level and - 3 V drive devices
P.W.
SD
DS
waveform
waveform
Peak Diode Recovery dV/dt Test Circuit
Body diode forward drop
Ripple ≤ 5 %
Period
Body diode forward
+
-
Fig. 14 - For P-Channel
• dV/dt controlled by R
• I
• D.U.T. - device under test
current
SD
Diode recovery
controlled by duty factor “D”
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
dV/dt
current transformer
dI/dt
D =
-
g
Period
P.W.
+
I
V
SD
V
GS
IRF9530S, SiHF9530S
DD
= - 10 V
+
-
V
DD
a
Vishay Siliconix
www.vishay.com
7