MTB2P50ET4G ON Semiconductor, MTB2P50ET4G Datasheet - Page 4

MOSFET P-CH 500V 2A D2PAK

MTB2P50ET4G

Manufacturer Part Number
MTB2P50ET4G
Description
MOSFET P-CH 500V 2A D2PAK
Manufacturer
ON Semiconductor
Datasheet

Specifications of MTB2P50ET4G

Fet Type
MOSFET P-Channel, Metal Oxide
Fet Feature
Standard
Rds On (max) @ Id, Vgs
6 Ohm @ 1A, 10V
Drain To Source Voltage (vdss)
500V
Current - Continuous Drain (id) @ 25° C
2A
Vgs(th) (max) @ Id
4V @ 250µA
Gate Charge (qg) @ Vgs
27nC @ 10V
Input Capacitance (ciss) @ Vds
1183pF @ 25V
Power - Max
2.5W
Mounting Type
Surface Mount
Package / Case
D²Pak, TO-263 (2 leads + tab)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MTB2P50ET4G
Manufacturer:
ROHM
Quantity:
30 000
Part Number:
MTB2P50ET4G
Manufacturer:
ON
Quantity:
12 500
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that
t = Q/I
During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V
times may be approximated by the following:
t
t
where
V
R
and Q
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
r
f
d(on)
d(off)
G
GG
= Q
= Q
Switching behavior is most easily modeled and predicted
1600
1400
1200
1000
1800
800
600
400
200
= the gate drive resistance
0
= the gate drive voltage, which varies from zero to V
= R
2
2
2
= R
10
G(AV)
x R
x R
and V
C
C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
G
iss
G
rss
V
G
G
DS
C
C
/(V
/V
iss
iss
= 0 V
5
GSP
Figure 7a. Capacitance Variation
GSP
GG
In [V
In (V
V
GS
GS
are read from the gate charge curve.
− V
0
remains virtually constant at a level
GG
GG
GSP
C
/(V
rss
/V
V
V
DS
GS
)
G(AV)
GSP
GG
5
= 0 V
)
− V
C
SGP
) can be made from a
oss
GSP
C
. Therefore, rise and fall
10
iss
)]
15
POWER MOSFET SWITCHING
T
J
20
= 25°C
http://onsemi.com
MTB2P50E
GG
25
4
The capacitance (C
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring which
is common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a
function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also complicates
the mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to
measure and, consequently, is not specified.
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1000
100
10
At high switching speeds, parasitic circuit elements
The resistive switching time variation versus gate
1
10
V
T
J
GS
= 25°C
Figure 7b. High Voltage Capacitance
= 0 V
d(on)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
and is read at a voltage corresponding to the
iss
) is read from the capacitance curve at
Variation
d(off)
100
.
C
C
C
iss
oss
rss
1000

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