MTB50P03HDLG ON Semiconductor, MTB50P03HDLG Datasheet - Page 6

• Manufacturer Part Number: MTB50P03HDLG
• Description: MOSFET P-CH 30V 50A D2PAK
• Manufacturer: ON Semiconductor

Specifications of MTB50P03HDLG

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 25 mOhm @ 25A, 5V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 50A
• Vgs(th) (max) @ Id: 2V @ 250µA
• Gate Charge (qg) @ Vgs: 100nC @ 5V
• Input Capacitance (ciss) @ Vds: 4900pF @ 25V
• Power - Max: 2.5W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MTB50P03HDLG; MTB50P03HDLGOS

the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
traverse any load line provided neither rated peak current
(I
transition time (t
total power averaged over a complete switching cycle must
not exceed (T
in switching circuits with unclamped inductive loads. For
DM
1000
The Forward Biased Safe Operating Area curves define
Switching between the off−state and the on−state may
A power MOSFET designated E−FET can be safely used
100
10
1
0.1
) nor rated voltage (V
V
SINGLE PULSE
T
C
GS
Figure 12. Maximum Rated Forward Biased
= 25°C
= 20 V
J(MAX)
V
DS
r
, t
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
f
) does not exceed 10 ms. In addition the
Safe Operating Area
− T
1.0
R
THERMAL LIMIT
PACKAGE LIMIT
C
DS(on)
)/(R
DSS
LIMIT
qJC
) is exceeded, and that the
).
10
di/dt = 300 A/ms
Figure 11. Reverse Recovery Time (t
SAFE OPERATING AREA
C
) of 25°C.
10 ms
100 ms
1 ms
dc
http://onsemi.com
MTB50P03HDL
100
6
t, TIME
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I
assumed to equal the values indicated.
1400
1000
1200
800
600
400
200
Although many E−FETs can withstand the stress of
0
25
Standard Cell Density
High Cell Density
Figure 13. Maximum Avalanche Energy versus
t
a
DM
t
rr
T
t
), the energy rating is specified at rated
J
rr
, STARTING JUNCTION TEMPERATURE (°C)
Starting Junction Temperature
t
50
b
rr
)
D
), in accordance with industry
75
100
D
125
I
D
can safely be
= 50 A
150