AD8611ARZ Analog Devices Inc, AD8611ARZ Datasheet - Page 6

• Manufacturer Part Number: AD8611ARZ
• Description: Comparator Single 5V 8-Pin SOIC N
• Manufacturer: Analog Devices Inc
• Type: with Latchr

Specifications of AD8611ARZ

• Package: 8SOIC N
• Typical Response Time Range: 0.0003 to 0.05 us
• Typical Voltage Gain Range: 40 to 70 dB
• Output Type: Complementary
• Number Of Channels Per Chip: 1
• Minimum Single Supply Voltage: 3 V
• Power Supply Type: Single
• Number Of Elements: 1
• Voltage - Supply: 2.7 V ~ 6 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Amplifier Type: Comparator
• Common Mode Rejection Ratio: 85
• Current, Input Bias: -4 μA
• Current, Input Offset: ±4 μA
• Current, Supply: -2.2 to +5.7 mA
• Impedance, Thermal: 158 °C/W
• Number Of Amplifiers: Quad
• Package Type: SOIC-8
• Propagation Delay: 4 ns
• Temperature, Operating, Range: -40 to +85 °C
• Time, Fall: 1.1 ns
• Time, Rise: 2.5 ns
• Voltage, Gain: 3000 V/V
• Voltage, Input: ±4 V
• Voltage, Input Offset: 1 mV
• Voltage, Supply: 3 to 5 V
• Comparator Type: High Speed
• No. Of Comparators: 1
• Response Time: 4ns
• Ic Output Type: CMOS, MOS, Open-Collector / Drain, TTL
• Supply Current: 5.7mA
• Rohs Compliant: Yes
• Output Compatibility: TTL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8611/AD8612
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
SOIC and
MSOP
1
2
3
4
5
6
7
8
Figure 4. 8-Lead Narrow Body SOIC Pin Configuration
IN+
IN–
V+
V–
Pin No.
1
2
3
4
(Not to Scale)
AD8611
TOP VIEW
TSSOP
10
5
3, 12
1
2
14
13
4
11
7
6
8
9
8
7
6
5
QA
QA
GND
LATCH
Mnemonic
V+
IN+
IN−
V−
LATCH
GND
QA
QA
QB
QB
LEA
LEB
INA+
INA−
INB+
INB−
Description
Positive Supply Terminal.
Noninverting Analog Input of the Differential Input Stage.
Inverting Analog Input of the Differential Input Stage.
Negative Supply Terminal.
Latch Enable Input.
Negative Logic Supply
One of Two Complementary Output for Channel A.
One of Two Complementary Output for Channel A.
One of Two Complementary Output for Channel B.
One of Two Complementary Output for Channel B.
Channel A Latch Enable.
Channel B Latch Enable.
Noninverting Analog Input of the Differential Input Stage for Channel A.
Inverting Analog Input of the Differential Input Stage for Channel A.
Noninverting Analog Input of the Differential Input Stage for Channel B.
Inverting Analog Input of the Differential Input Stage for Channel B.
Figure 5. 8-Lead MSOP Pin Configuration
IN+
IN–
V+
V–
1
2
3
4
Rev. A | Page 6 of 20
(Not to Scale)
TOP VIEW
AD8611
8
7
6
5
QA
QA
GND
LATCH
Figure 6. 14-Lead TSSOP Pin Configuration
GND
INA–
INA+
LEA
QA
QA
V–
1
2
3
4
5
6
7
(Not to Scale)
AD8612
TOP VIEW
14
13
12
11
10
9
8
QB
GND
LEB
V+
INB–
INB+