ZL30407QCG1 Zarlink, ZL30407QCG1 Datasheet

ZL30407QCG1

Manufacturer Part Number

ZL30407QCG1

Description

PB FREE SONET/SDH NETWORK ELEMENT PLL

Manufacturer

Zarlink

Datasheets

1.ZL30407QCG1.pdf (57 pages)

2.ZL30407QCG1.pdf (57 pages)

3.ZL30407QCG1.pdf (57 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ZL30407QCG1

Manufacturer:

ZARLINK

Quantity:

345

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Features

•

SECOR

PRIOR

Meets requirements of GR-253 for SONET

Stratum 3 and SONET Minimum Clocks (SMC)

Meets requirements of GR-1244 for Stratum 3

Meets requirements of G.813 Option 1 and 2 for

SDH Equipment Clocks (SEC)

Generates clocks for ST-BUS, DS1, DS2, DS3,

OC-3, E1, E3, STM-1 and 19.44 MHz

Holdover accuracy of 4x10

Stratum 3E and ITU-T G.812 requirements

Continuously monitors both references for

frequency accuracy exceeding ±12 ppm

Provides “hit-less” reference switching

Compensates for Master Clock Oscillator

accuracy

Automatically detects frequency of both reference

clocks and synchronizes to any combination of

8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz

reference frequencies

Allows Hardware or Microprocessor control

Pin compatible with ZL30410, ZL30402 and

MT90401

RefSel

SEC

RESET

PRI

Acquisition

Secondary

Acquisition

VDD GND

Primary

PLL

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

R/W

Microport

A0-A6

-12

D0-D7

meets GR-1244

Master Clock

Calibration

Frequency

Figure 1 - Functional Block Diagram

MUX

C20i

Zarlink Semiconductor Inc.

MS1 MS2

Control State Machine

Core PLL

Applications

•

Description

The ZL30407 is a Network Element Phase-Locked

Loop designed to synchronize SDH and SONET

systems. In addition, it generates multiple clocks for

legacy PDH equipment and provides timing for ST-

BUS and GCI backplanes.

SONET/SDH Network Element PLL

Synchronization for SDH and SONET Network

Elements

Clock generation for ST-BUS and GCI backplanes

ZL30407QCC

ZL30407QCG1

RefAlign

FCS

LOCK

Ordering Information

HOLDOVER

*Pb Free Matte Tin

80 Pin LQFP Trays

80 Pin LQFP* Trays, Bake & Drypack

Synthesizer

-40qC to +85qC

APLL

Clock

1149.1a

JTAG

IEEE

E3/DS3

E3DS3/OC3

Data Sheet

C155P/N

C34/C44

C19o

C16o

C8o

C6o

C4o

C2o

C1.5o

F16o

F8o

F0o

Tclk

Tdi

Tdo

Tms

ZL30407

Trst

November 2006

R1-17

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