ZL30407QCG1 Zarlink, ZL30407QCG1 Datasheet - Page 25

• Manufacturer Part Number: ZL30407QCG1
• Description: PB FREE SONET/SDH NETWORK ELEMENT PLL
• Manufacturer: Zarlink

4.2.3
Address: 00 H
6-5
4-3
Bit
7
2
1
0
Register Description
MS2, MS1
RefAlign
RefSel
Name
RSV
FCS
RSV
Reference Select. A zero selects the PRI (Primary) reference source
as the input reference signal and a one selects the SEC (secondary)
reference.
Reserved
Mode Select
Filter Characteristic Select (see Table 12 on page 29 for
complimentary FCS2 bit description)
Conformance of these filter settings to standards is presented in
Table 1, “Loop Filter Selection” on page 13.
Reserved
Reference Alignment. A high-to-low transition aligns the generated
output clocks to the input reference signal (see Section 3.2.5,
Reference Alignment (RefAlign) for details). This bit should never be
held low permanently.
-
-
-
-
-
-
-
-
MS2 = 0 MS1 = 0
MS2 = 0 MS1 = 1
MS2 = 1 MS1 = 0
MS2 = 1 MS1 = 1
FCS2 = 0, FCS = 0 : Filter corner frequency set to 1.5 Hz.
FCS2 = 0, FCS = 1 : Filter corner frequency set to 0.1 Hz.
FCS2 = 1, FCS = 0 : Filter corner frequency set to 12 Hz.
FCS2 = 1, FCS = 1 : Filter corner frequency set to 6 Hz.
Table 6 - Control Register 1 (R/W)
Zarlink Semiconductor Inc.
ZL30407
Functional Description
25
Normal Mode (Locked Mode)
Holdover Mode
Free-run Mode
Reserved
Data Sheet
Default
00
10
0
0
0
1