MT8952BP1 Zarlink, MT8952BP1 Datasheet - Page 21

• Manufacturer Part Number: MT8952BP1
• Description: PB FREE HDLC CONTROLLER, PLCC
• Manufacturer: Zarlink

AC Electrical Characteristics
Voltages are with respect to ground (V
† Timing is over recommended temperature & power supply voltages (V
‡ Typical figures are at 25
Note: The frequency of the clock input (CKi) should be at the output bit rate in the External Timing Mode.
CKi
TxCEN/
RxCEN
CDSTi
CDSTo
1
2
3
4
5
6
7
8
F0i
ST-BUS
Clock period on CKi pin
CKi transition time
TxCEN/RxCEN setup time
TxCEN/RxCEN hold time
CDSTi setup time
CDSTi hold time
CDSTo delay
CDSTo disable time
Channel
Characteristics
31
HIGH IMPEDANCE
°
Figure 23 - Serial Port Inputs and Outputs in External Timing Mode
C and are for design aid only: not guaranteed and not subject to production testing.
Channel
0
t
t
CENS
T
(D0 on the Data
SS
Channel
) unless otherwise stated.
1
Significant
t
t
†
SToZL
SToZH
- Serial Port in External Timing Mode - (Figure 23 )
t
t
Least
t
t
t
t
Sym
t
SToZH
SToHZ
Bus)
CENS
CENH
t
SToZL
SToLZ
t
STiS
STiH
CEX
t
CENH
t
Bit
T
Channel
Figure 24 - ST-BUS Format
2
Bit 7
Min
400
60
40
20
65
• • • • • • • •
Bit 6
VALID DATA
t
STiS
125 µsec
DD
Typ
t
20
CEX
=5V
Bit 5
‡
±
5%, V
t
STiH
Max
Bit 4
125
85
SS
3.9 µsec
=0V, T
Channel
Bit 3
29
Units
A
ISO-CMOS
=–40 to 85
ns
ns
ns
ns
ns
ns
ns
ns
Bit 2
Channel
Test load circuit 1 (Fig. 26)
C
Test load circuit 3 (Fig. 26)
30
°
Bit 1
L
C).
=150pF
Test Conditions
Channel
Bit 0
t
t
SToHZ
SToLZ
31
MT8952B
Most
Significant
Bit
(D7 on the Data
Bus)
Channel
HIGH
IMPEDANCE
0
3-81