AD9200ARS Analog Devices Inc, AD9200ARS Datasheet
AD9200ARS
Specifications of AD9200ARS
Available stocks
Related parts for AD9200ARS
AD9200ARS Summary of contents
Page 1
... The versatile SHA input can be configured for either single- ended or differential inputs. Out-of-Range Indicator The OTR output bit indicates when the input signal is beyond the AD9200’s input range. Built-In Clamp Function Allows dc restoration of video signals with AD9200ARS and AD9200KST. FUNCTIONAL BLOCK DIAGRAM CLAMP IN CLK ...
Page 2
AD9200–SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage 1 Reference Input Resistance ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture ...
Page 3
... Low Level Output Voltage ( CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency 2 CLAMP Clamp Error Voltage Clamp Pulsewidth NOTES 1 See Figures 1a and 1b. 2 Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice. REFTS REFBS MODE AV DD REV. E Symbol Min Typ Max V 2 ...
Page 4
... AD9200JRS AVDD + 0.3 V AD9200ARS DRVDD + 0.3 V AD9200JST AVDD + 0.3 V AD9200KST AVDD + 0.3 V AD9200JRSRL AVDD + 0.3 V AD9200ARSRL – +85 C 28-Lead SSOP (Reel) RS-28 AVDD + 0.3 V AD9200JSTRL AVDD + 0.3 V AD9200KSTRL +70 C +150 C AD9200 SSOP-EVAL +150 C AD9200 LQFP-EVAL *RS = Shrink Small Outline Thin Quad Flatpack. ...
Page 5
Shrink Small Outline (SSOP) AVDD AVSS 1 28 DRVDD 2 AIN VREF D1 4 REFBS REFBF AD9200 MODE TOP VIEW (Not to Scale REFTF 8 ...
Page 6
AD9200 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used as “zero” occurs 1/2 LSB before the first code transi- tion. ...
Page 7
AMPLITUDE –45 –50 –6.0 AMPLITUDE –55 –60 –65 –0.5 AMPLITUDE –70 –75 –80 1.00E+05 1.00E+06 INPUT FREQUENCY – Hz Figure 7. THD vs. Input Frequency – 1MHz –60 IN –50 –40 –30 –20 –10 ...
Page 8
AD9200 0 –3 –6 –9 –12 –15 –18 –21 –24 –27 1.0E+6 10.0E+6 100.0E+6 FREQUENCY – Hz Figure 13. Full Power Bandwidth –5 –10 –15 –20 –25 0 0.5 1.0 1.5 INPUT VOLTAGE – ...
Page 9
SUMMARY OF MODES VOLTAGE REFERENCE 1 V Mode the internal reference may be set connect- ing REFSENSE and VREF together Mode the internal reference my be set connecting REFSENSE to ...
Page 10
AD9200 +FS AIN –FS SHA +F/S RANGE OBTAINED FROM VREF PIN OR 10k EXTERNAL REF 10k REFTS A2 REFBS A/D CORE 10k –F/S RANGE OBTAINED 10k FROM VREF PIN OR EXTERNAL REF a. Top/Bottom Mode MAXIMUM MAGNITUDE ...
Page 11
The actual reference voltages used by the internal circuitry of the AD9200 appear on REFTF and REFBF. For proper opera- tion necessary to add a capacitor network to decouple these pins. The REFTF and REFBF should be decoupled ...
Page 12
... The ADC will “wake up” in 400 ns (typ) after the standby pulse goes low. AD9200 CLAMP OPERATION AVDD AVDD The AD9200ARS and AD9200KST parts feature an optional clamp circuit for dc restoration of video or ac coupled signals. 0.1 F REFTF Figure 24 shows the internal clamp circuitry and the external 0.1 F control signals needed for clamp operation ...
Page 13
The input capacitor should be sized to allow sufficient acquisi- tion time of the clamp voltage at AIN within the CLAMP inter- val, but also be sized to minimize droop between clamping intervals. Specifically, the acquisition time when the switch ...
Page 14
AD9200 DRIVING THE ANALOG INPUT Figure 25 shows the equivalent analog input of the AD9200, a sample-and-hold amplifier (switched capacitor input SHA). Bringing CLK to a logic low level closes Switches 1 and 2 and opens Switch 3. The input ...
Page 15
DIFFERENTIAL INPUT OPERATION The AD9200 will accept differential input signals. This function may be used by shorting REFTS and REFBS and driving them as one leg of the differential signal (the top leg is driven into AIN). In the configuration ...
Page 16
AD9200 APPLICATIONS DIRECT IF DOWN CONVERSION USING THE AD9200 Sampling IF signals above an ADC’s baseband region (i.e /2) is becoming increasingly popular in communication S applications. This process is often referred to as Direct IF Down ...
Page 17
Figures 35–38 combine the dual-tone SFDR as well as single tone SFDR and SNR performance at IF frequencies of 45 MHz, 70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli- tude data is referenced to dBFS while ...
Page 18
AD9200 R10 15k 5k +3–5A TP14 R7 2 5.49k XXXX ADJ 10k AD1580 10/10V R9 1.5k XXXX ADJ. R14 10k CW J7 JP5 R37 1k R53 49.9 JP17 R38 1k GND JP18 R39 1k AVDD ...
Page 19
JP1 AVDD C3 JP2 0.1 F TP1 C5 10/10V JP3 JP9 JP4 VREF TP5 JP11 TP6 A JP6 JP12 C35 10/10V TP7 JP7 JP13 T1– ...
Page 20
AD9200 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) –20– REV. E ...
Page 21
Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9200 ...
Page 22
AD9200 Figure 40e. Evaluation Board Component Silk (Not to Scale) Figure 40f. Evaluation Board Solder Silk (Not to Scale) –22– REV. E ...
Page 23
GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9200 have been separated to optimize the management ...
Page 24
AD9200 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.053 ...