AD7398BRU Analog Devices Inc, AD7398BRU Datasheet - Page 4

• Manufacturer Part Number: AD7398BRU
• Description: DAC 4-CH R-2R 12-Bit 16-Pin TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7398BRU

• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 167 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI)
• Number Of Outputs Per Chip: 4
• Output Type: Voltage
• Full Scale Error: ±2.5 mV
• Integral Nonlinearity Error: ±1.5 LSB
• Maximum Settling Time: 6(Typ) us
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 16mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

AD7398/AD7399
Parameter
SUPPLY CHARACTERISTICS
1
2
3
4
5
6
7
8
AD7399 10-BIT VOLTAGE OUTPUT DAC
V
Table 2.
Parameter
STATIC PERFORMANCE
REFERENCE INPUT
ANALOG OUTPUT
LOGIC INPUTS
INTERFACE TIMING
One LSB = V
The first eight codes (000
These parameters are guaranteed by design and not subject to production testing.
When V
voltage of the output buffer, which is the same as the V
Input resistance is code dependent.
Typicals represent average readings measured at 25°C.
All input control signals are specified with t
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
DD
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco
V
Input Resistance
Input Capacitance
Output Voltage Range
Output Current
Capacitive Load
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup to CS
Load Hold to CS
REF
= 5 V, V
IN Range
REF
is connected to either the V
REF
SS
/4096 V for the 12-bit AD7398.
1
= 0 V; or V
4
3
3, 7
5
2
3
3
3
H
to 007
DD
2
H
= +5 V, V
) are excluded from the linearity error measurement in single-supply operation.
DD
Symbol
I
I
I
I
P
PSS
Symbol
N
INL
DNL
V
V
TCV
V
R
C
V
I
C
V
V
I
C
f
t
t
t
t
t
t
t
t
t
DD_SD
DD
DD
SS
OUT
IL
or the V
CLK
CH
CL
CSS
CSH
LDAC
DS
DH
LDS
LDH
DISS
REF
ZSE
FSE
REF
REF
OUT
L
IL
IH
IL
R
FS
= t
SS
F
= –5 V; V
SS
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
power supply, the corresponding V
ZSE
Condition
No load
V
V
V
ΔV
V
IL
IL
IL
IL
error specification. See additional information in the Theory of Operation section.
= 0 V, no load, −40°C < T
REF
= 0 V, no load
= 0 V, no load
DD
= 0 V, no load, −40°C < T
Condition
Monotonic
Data = 000
Data = 3FF
Data = 155
Data = 200
No oscillation
V
V
CLK only
DD
DD
= ±5%
= +2.5 V, −40°C < T
= 3 V
= 5 V
H
H
H
H
Rev. C | Page 4 of 24
, worst case
, ΔV
OUT
= 1 LSB
OUT
A
A
< +125°C
A
voltage programs between ground and the supply voltage minus the offset
< +125°C, unless otherwise noted.
< +85°C
3 V to 5 V ± 10%
30/60
1.5/2.8
1.5/2.6
1.5/2.5
5
0.006
3 V to 5 V ± 10%
10
±1
±1
7
±15
1.5
0/V
40
5
0 to V
±5
200
0.5
0.8
80% V
2.1 to 2.4
1
10
11
45
45
10
20
45
15
10
0
20
DD
REF
DD
±5 V ± 10%
30/60
1.6/3
1.6/2.8
1.6/2.7
16
0.006
±5 V ± 10%
10
±1
±1
±4
±15
1.5
V
40
5
0 to V
±5
400
0.8
4.0
2.4
1
10
16.6
30
30
5
15
30
10
5
0
15
SS
/V
DD
REF
Unit
μA typ/max
mA typ/max
mA typ/max
mA typ/max
mW typ
%/% max
Unit
Bits
LSB max
LSB max
mV max
mV max
ppm/°C typ
V min/max
kΩ typ
pF typ
V
mA typ
pF max
V max
V max
V min
V min
μA max
pF max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
6