AD9764AR Analog Devices Inc, AD9764AR Datasheet - Page 7
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AD9764AR
Manufacturer Part Number
AD9764AR
Description
DAC 1-CH Segment 14-Bit 28-Pin SOIC W
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet
1.AD9764ARZ.pdf
(22 pages)
Specifications of AD9764AR
Package
28SOIC W
Resolution
14 Bit
Conversion Rate
125 MSPS
Architecture
Segment
Digital Interface Type
Parallel
Number Of Outputs Per Chip
1
Output Type
Current
Full Scale Error
±7 %FSR
Integral Nonlinearity Error
±6.5 LSB
Maximum Settling Time
0.035(Typ) us
Rohs Status
RoHS non-compliant
Settling Time
35ns
Number Of Bits
14
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
170mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
For Use With
AD9764-EB - BOARD EVAL FOR AD9764
Data Interface
-
Lead Free Status / RoHS Status
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Part Number
Manufacturer
Quantity
Price
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Typical AC Characterization Curves
(AVDD = +5 V, DVDD = +3 V, I
REV. B
Figure 9. Single-Tone SFDR vs. A
@ f
Figure 6. SFDR vs. f
Figure 3. SFDR vs. f
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
55
50
45
40
OUT
90
80
70
60
50
0.1
–30
0
5 MSPS
2.27MHz @ 25 MSPS
= f
25 MSPS
–25
CLOCK
–6dBFS
5
50 MSPS
0dBFS
4.55MHz @ 50 MSPS
FREQUENCY – MHz
FREQUENCY – MHz
–20
100 MSPS
1
/11
A
10
OUT
455kHz @ 5 MSPS
–12dBFS
9.09MHz @ 100 MSPS
–15
– dBFS
OUT
15
OUT
–10
10
OUTFS
@ 50 MSPS
@ 0 dBFS
20
= 20 mA, 50
–5
100
25
0
OUT
Doubly Terminated Load, Differential Output, T
Figure 7. SFDR vs. f
Figure 4. SFDR vs. f
Figure 10. Single-Tone SFDR vs.
A
90
85
80
75
70
65
60
55
50
45
40
OUT
90
85
80
75
70
65
60
55
50
45
40
90
80
70
60
50
–30
0
0
@ f
5MHz @ 25 MSPS
0dBFS
10MHz @ 50 MSPS
–25
0.5
OUT
10
1MHz @ 5 MSPS
–12dBFS
0dBFS
–6dBFS
FREQUENCY – MHz
FREQUENCY – MHz
–20
= f
A
1.0
20
–7–
OUT
CLOCK
–15
20MHz @ 100 MSPS
– dBFS
–6dBFS
OUT
–12dBFS
1.5
/5
OUT
30
–10
@100 MSPS
@ 5 MSPS
2.0
40
–5
2.5
50
0
A
= +25 C, SFDR up to Nyquist, unless otherwise noted)
Figure 11. Dual-Tone SFDR vs. A
@ f
Figure 5. SFDR vs. f
90
85
80
75
70
65
60
55
50
90
80
70
60
50
OUT
90
85
80
75
70
65
60
55
50
45
40
0.0
Figure 8. SFDR vs. f
I
–30
OUTFS
0
0.675/0.725MHz @ 5 MSPS
= f
–25
CLOCK
2
2.0
20mA @ 5V
@ 25 MSPS and 0 dBFS
–6dBFS
20mA @ 3V
FREQUENCY – MHz
FREQUENCY – MHz
–20
6.75/7.25 @ 50 MSPS
0dBFS
/7
4
A
4.0
3.38/3.63MHz @ 25 MSPS
OUT
13.5/14.5MHz @ 100 MSPS
–12dBFS
–15
6
– dBFS
5mA @ 3V
5mA @ 5V
OUT
6.0
AD9764
–10
8
10mA @ 3V
@ 25 MSPS
10mA @ 5V
OUT
8.0
and
–5
10
10.0
12
OUT
0