74ABT125D NXP Semiconductors, 74ABT125D Datasheet

Buffer/Line Driver 4-CH Non-Inverting 3-ST BiCMOS 14-Pin SO Tube

74ABT125D

Manufacturer Part Number
74ABT125D
Description
Buffer/Line Driver 4-CH Non-Inverting 3-ST BiCMOS 14-Pin SO Tube
Manufacturer
NXP Semiconductors
Datasheets

Specifications of 74ABT125D

Package
14SO
Logic Family
ABT
Logic Function
Buffer/Line Driver
Number Of Outputs Per Chip
4
Output Type
3-State
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum Cl
4.6@5V ns
Polarity
Non-Inverting
Supply Voltage Range
4.5V To 5.5V
Logic Case Style
SOIC
No. Of Pins
14
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (18-Jun-2010)
Base Number
74
Ic Generic
RoHS Compliant
Package / Case
SOIC
Logic Device Type
Buffer, Non Inverting
Rohs Compliant
Yes
No. Of Circuits
4
Lead Free Status / RoHS Status

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT125D
Quantity:
49
Part Number:
74ABT125D
Manufacturer:
ST
0
Part Number:
74ABT125D
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74ABT125D
Manufacturer:
NXP
Quantity:
12 318
Part Number:
74ABT125D
Quantity:
138
Company:
Part Number:
74ABT125DB
Quantity:
2 000
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74ABT125N
74ABT125D
74ABT125DB
74ABT125PW
74ABT125BQ
Ordering information
Package
Temperature range
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
The 74ABT125 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device
features four Output Enables (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state
outputs.
74ABT125
Quad buffer; 3-state
Rev. 5 — 24 November 2010
Quad bus interface
3-state buffers
Live insertion and extraction permitted
Output capability: HIGH 32 mA; LOW +64 mA
Power-up 3-state
Inputs are disabled during 3-state mode
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Name
DIP14
SO14
SSOP14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
plastic thin shrink small outline package; 14 leads;
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
body width 4.4 mm
thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
Product data sheet
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
SOT762-1

Related parts for 74ABT125D

74ABT125D Summary of contents

Page 1

... Ordering information Type number Package Temperature range 40 C to +85 C 74ABT125N 40 C to +85 C 74ABT125D 40 C to +85 C 74ABT125DB 40 C to +85 C 74ABT125PW 40 C to +85 C 74ABT125BQ Name Description DIP14 plastic dual in-line package; 14 leads (300 mil) SO14 plastic small outline package ...

Page 2

... NXP Semiconductors 4. Functional diagram 1OE 2OE 3OE 4OE 13 mna228 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74ABT125 1OE 2OE GND 7 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 74ABT125 Product data sheet EN1 mna229 Fig 2. IEC logic symbol 4OE 3OE 001aai027 Fig 5. ...

Page 3

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 1OE to 4OE GND Functional description [1] Table 3. Function selection Inputs nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values [1] Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). ...

Page 4

... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V HIGH-level input voltage IH V LOW-level Input voltage IL I HIGH-level output current OH I LOW-level output current OL t/V input transition rise and fall rate ...

Page 5

... NXP Semiconductors Table 6. Static characteristics Symbol Parameter I additional supply CC current C input capacitance I C output capacitance O [1] This parameter is valid for any V a transition time 100 s is permitted. [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ...

Page 6

... NXP Semiconductors 11. Waveforms and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay input (nA) to output (nY) nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH and V are typical voltage output levels that occur with the output load. ...

Page 7

... NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data is given in Table Test circuit definitions Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 8. Load circuitry for switching times Table 8 ...

Page 8

... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 9

... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 11. Package outline SOT337-1 (SSOP14) ...

Page 11

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS BipolarCMOS DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date 74ABT125 v.5 20101124 • Modifications: Figure note [1] 74ABT125 v.4 20100427 74ABT125 v.3 20080429 74ABT125 v ...

Page 14

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 15

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ABT125 Product data sheet 15 ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations ...

Related keywords