SI5323-C-GM Silicon Laboratories Inc, SI5323-C-GM Datasheet
SI5323-C-GM
Specifications of SI5323-C-GM
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SI5323-C-GM Summary of contents
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... The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates ...
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... Si5323 2 Rev. 1.0 ...
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... Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Pin Descriptions: Si5323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. Si5323 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Contact Information ...
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... Si5323 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. ...
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... CMOS CMOS IO Driving into CKO for out- VOL put low or CKO for output VOH high. CKOUT+ and CKOUT– shorted externally 1 3 > 2 Rev. 1.0 Si5323 Min Typ Max Units 0.2 — — 0.25 — — – — V – 1.42 1 ...
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... Si5323 Table 2. DC Characteristics (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol 2-Level LVCMOS Input Pins Input Voltage Low V Input Voltage High V Input Low Current I Input High Current I Weak Internal Input Pull-up R PUP Resistor Weak Internal Input R PDN Pull-down Resistor ...
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... RIN RATE[1:0] = LM, ML, MH, or VIN HM VPP XTAL/RefCLK RIN RATE[1:0] = LM, ML, MH, or VIN HM /XB VPP > 2 ISE Figure 1. Voltage Characteristics Rev. 1.0 Si5323 Min Typ Max Units — — 0.4 — — 0.4 V – 0.4 — — – 0.4 — — DD –100 — ...
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... Si5323 CKIN, CKOUT Figure 2. Rise/Fall Time Characteristics Rev. 1.0 80% 20% ...
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... Figure 3. Three-Level Input Pins V DD Si5323 18 k 3L input current 18 k Figure 4. Three-Level Input Pins 1,2,3,4 Min –30 µA –11 µA — Panasonic EXB-D10C183J). PCB layout is not critical resistors are needed. Rev. 1.0 Si5323 k 75 k Max — –11 µA –30 µA 9 ...
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... Si5323 Table 4. AC Characteristics (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter CKIN Input Pins Input Frequency Input Duty Cycle (Minimum Pulse Width) Input Capacitance Input Rise/Fall Time CKOUTn Output Pins Output Frequency (Output not configured for CMOS or disable) Maximum Output Frequency in ...
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... MHz 12 kHz–20 MHz 800 Hz–80 MHz 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time OUT Rev. 1.0 Si5323 Min Typ Max Units — 1.2 sec — 200 — ...
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... Si5323 Table 6. Thermal Characteristics (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Thermal Resistance JA Junction to Ambient Thermal Resistance JC Junction to Case Table 7. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage CKINn Voltage Level Limits XA/XB Voltage Level Limits Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ ...
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... Typical Phase Noise Plots The following is the typical phase noise performance of the Si5323. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The phase noise analyzer was an Agilent model E5052B. The Si5323 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm ...
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... Bandwidth Select 15 k Skew Increment Skew Decrement k Signal Format Select k 15 k Clock Output 2 Disable/ Bypass Mode Control 15 k Reset Notes: Figure 6. Si5323 Typical Application Circuit µF 4 System C 0.1 µF 3 Power Ferrite Supply Bead C 0.1 µ 0.1 µF ...
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... Manual and automatic revertive and non-revertive input clock switching options are available via the AUTOSEL input pin. The Si5323 monitors both input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on either input clock ...
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... Si5323 3.3. Frequency Plan Tables The Si5323 provides flexible frequency plans for SONET, Datacom, and interworking between the two (Table 8, Table 9, and Table 10 respectively). Both CKINn inputs must be the same Fin frequency and CKOUTn outputs as specified in the tables. The following notes apply to Tables 8, 9, and 10: 1 ...
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... Rev. 1.0 Si5323 17 ...
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... Si5323 Table 8. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) Plan # FRQSEL [3:0] 52 MHHM 53 MMHM 54 MHHH 55 MHML 56 HLLL 57 MMHM 58 HLLM 59 MHML 60 HLLH 61 MMHM 62 HLML 63 MHML 64 HLMM 65 HLMH 66 HLHL 67 HLHM 68 HLHH 69 HMLL 70 HMLM 71 HMLH 72 HMML 73 HMMM 74 HMMH 75 HMHL 76 HMHM 77 HMHH 78 HHLL 79 HMML 80 HHLM 81 HMMH ...
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... Rev. 1.0 Si5323 19 ...
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... Si5323 Table 9. Datacom Clock Multiplication Settings (FRQTBL = M) (Continued) Plan # FRQSEL[3:0] 23 LHMH 24 LHHL 25 LHHM 26 LHHH 27 MLLL 28 MLLM 29 MLLH 30 MLML 31 MLMM 32 MLMH 33 MLHL 34 MLHM 35 MLHH 36 MMLL 37 MMLM 38 MMLH 39 MMML 40 MMMM 41 MMMH 42 MMHL 43 MMHM 44 MMHH 45 MHLL 46 MMMM 47 MMMH 48 MMHL 49 MMHM 50 MMHH 51 MHLL 52 MHLM 53 MHLH ...
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... Rev. 1.0 Si5323 21 ...
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... Si5323 Table 9. Datacom Clock Multiplication Settings (FRQTBL = M) (Continued) Plan # FRQSEL[3:0] 96 HMHH 97 HHLL 98 HHLM 99 HMML 100 HHLH 101 HMMM 102 HHML 103 HHMM 104 HHMH 105 HMML 106 HHHL 107 HMMM 108 HHHM 109 HHLL 110 HHLM 111 HMML 112 HHLH 113 ...
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... Table 10. SONET to Datacom Clock Multiplication Settings Plan # FRQSEL[3:0] f (MHz LLLL 0.008 1 LLLM 2 LLLH 3 LLML 4 LLMM 5 LLMH 6 LLHL 7 LLHM 8 LLHH 9 LMLL Rev. 1.0 Si5323 Mult Factor f * (MHz) OUT 3125 25 6480 51.84 53125/8 53.125 15625/2 62.5 53125/4 106.25 15625 125 78125/4 156.25 159375/8 159.375 53125/2 212.5 53125 425 23 ...
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... Si5323 Table 10. SONET to Datacom Clock Multiplication Settings (Continued) Plan # FRQSEL[3: (MHz) Mult Factor IN LMLM 19.440 625/486 LMLH 10625/3888 LMML 3125/972 LMMM 10625/1944 LMMH 3125/486 LMHL 15625/1944 LMHM 31875/3888 LMHH 15625/1944 x 66/64 LHLL 31875/3888 x 66/64 LHLM 15625/1944 x 66/64 x 255/23 8 LHLH 31875/3888 x 66/64 x 255/23 ...
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... Rev. 1.0 Si5323 25 ...
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... Si5323 Table 10. SONET to Datacom Clock Multiplication Settings (Continued) Plan # FRQSEL[3: (MHz) Mult Factor IN MHHM 155.520 15625/15552 MHHH 31875/31104 HLLL 15625/15552 x 66/64 HLLM 31875/31104 x 66/64 HLLH 15625/15552 x 66/64 x 255/2 38 HLML 31875/31104 x 66/64 x 255/2 38 HLMM 10625/7776 HLMH 10625/3888 HLHL 15625/3888 x 66/64 HLHM 31875/7776 x ...
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... BWSEL0 23 BWSEL1 24 FRQSEL0 25 FRQSEL1 26 FRQSEL2 27 FRQSEL3 30 SFOUT1 33 SFOUT0 Table 11. Si5323 Pins and Reset Must Reset after Changing Yes Yes No Yes No No Yes Yes Yes Yes Yes Yes No, but skew not guaranteed without Reset No, but skew not guaranteed without Reset Rev. 1.0 ...
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... Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5323 will perform an internal self-calibration when a valid input signal is present. This pin has a weak pull-up. ...
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... Table 12. Si5323 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 4 C2B GND GND 9 AUTOSEL I 11 RATE0 I 15 RATE1 12 CKIN2 CKIN2– LVCMOS CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated ...
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... Si5323 Table 12. Si5323 Pin Descriptions (Continued) Pin # Pin Name I/O 14 DBL2_BY I 16 CKIN1 CKIN1– 18 LOL O 19 DEC I 20 INC I 30 Signal Level 3-Level Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode CKOUT2 enabled M = CKOUT2 disabled ...
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... Table 12. Si5323 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 21 CS_CA I/O 23 BWSEL1 I 22 BWSEL0 27 FRQSEL3 I 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 29 CKOUT1– CKOUT1+ LVCMOS Input Clock Select/Active Clock Indicator. Input: If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector ...
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... Si5323 Table 12. Si5323 Pin Descriptions (Continued) Pin # Pin Name I/O 33 SFOUT0 I 30 SFOUT1 34 CKOUT2– CKOUT2 — GND GND GND PAD 32 Signal Level 3-Level Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for both CKOUT1 and CKOUT2 ...
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... Ordering Guide Ordering Part Number Si5323-C-GM 36-Lead QFN Si5322/23-EVB Evaluation Board Note: Add an “R” at the end of the device to denote tape and reel option (i.e., Si5323-C-GMR). Package Outline: 36-Pin QFN Package ROHS6, Pb-Free Yes Rev. 1.0 Si5323 Temperature Range – °C ...
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... Si5323 6. Package Outline: 36-Pin QFN Figure 7 illustrates the package details for the Si5323. Table 13 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min A 0.80 A1 0.00 b 0.18 D 6.00 BSC D2 3.95 e 0.50 BSC E 6 ...
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... Recommended PCB Layout Figure 9. Ground Pad Recommended Layout Figure 8. PCB Land Pattern Diagram Rev. 1.0 Si5323 35 ...
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... Si5323 Table 14. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... Si5323 Device Top Mark Laser Mark Method: 0.80 mm Font Size: Right-Justified Si5323 Line 1 Marking: C-GM Line 2 Marking: YYWWRF Line 3 Marking: Pin 1 Identifier Line 4 Marking: XXXX Customer Part Number See Ordering Guide for options C = Product Revision G = Temperature Range – °C (RoHS6 QFN Package ...
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... Si5323 N : OTES 38 Rev. 1.0 ...
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... Updated Table 1 on page 4. Updated Table 7 on page 12. Added table under Figure 5 on page 13. Updated 3. "Functional Description" on page 15. Clarified 4. "Pin Descriptions: Si5323" on page 28 including pull-up/pull-down. Updated SFOUT values. Revision 0.3 to Rev 1.0 Updated feature list on page 1. ...
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... Si5323 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Internet: www.silabs.com Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. ...