SI5323-C-GM Silicon Laboratories Inc, SI5323-C-GM Datasheet - Page 31

• Manufacturer Part Number: SI5323-C-GM
• Description: PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATO
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5323-C-GM

• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.05GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 1GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin #
21
23
22
27
26
25
24
29
28
Pin Name
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
CKOUT1–
CKOUT1+
BWSEL1
BWSEL0
CS_CA
I/O
I/O
Table 12. Si5323 Pin Descriptions (Continued)
O
I
I
Signal Level
LVCMOS
3-Level
3-Level
Multi
Input Clock Select/Active Clock Indicator.
Input: If manual clock selection mode is chosen
Output: If automatic clock selection mode is chosen
Bandwidth Select.
Three level inputs that select the DSPLL closed loop
bandwidth. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision
Clock Family Reference Manual.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Multiplier Select.
Three level inputs that select the input clock and clock
multiplication ratio, depending on the FRQTBL setting.
Consult the Any-Frequency Precision Clock Family
Reference Manual or DSPLLsim configuration software for
settings, both available for download at
www.silabs.com/timing
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
Rev. 1.0
(AUTOSEL = L), this pin functions as the manual input
clock selector. This input is internally deglitched to
prevent inadvertent clock switching during changes in
the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as an input, this pin must be set high or
low.
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If alarms
exist on both CKIN1 and CKIN2, indicating that the
digital hold state has been entered, CA will indicate
the last active clock that was used before entering the
hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
(click on Documentation).
Description
Si5323
31