74LVC1G79GW-G NXP Semiconductors, 74LVC1G79GW-G Datasheet

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74LVC1G79GW-G

Manufacturer Part Number
74LVC1G79GW-G
Description
Flip Flop D-Type Pos-Edge 1-Element 5-Pin TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G79GW-G

Package
5TSSOP
Logic Function
D-Type
Logic Family
LVC
Number Of Elements Per Chip
1
Output Signal Type
Single-Ended
Typical Operating Supply Voltage
1.8|2.5|3.3|5 V
Operating Temperature
-40 to 125 °C
1. General description
2. Features and benefits
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition
of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
74LVC1G79
Single D-type flip-flop; positive-edge trigger
Rev. 8 — 30 September 2010
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
ESD protection:
±24 mA output drive (V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C.
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

Related parts for 74LVC1G79GW-G

74LVC1G79GW-G Summary of contents

Page 1

Single D-type flip-flop; positive-edge trigger Rev. 8 — 30 September 2010 1. General description The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the ...

Page 2

... Marking Table 2. Marking codes Type number 74LVC1G79GW 74LVC1G79GV 74LVC1G79GM 74LVC1G79GF 74LVC1G79GN 74LVC1G79GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 ...

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... NXP Semiconductors CP D Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC1G79 GND Q 001aaf188 Fig 4. Pin configuration SOT353-1 and SOT753 6.2 Pin description Table 3. Pin description Symbol Pin SOT353-1, SOT753 GND n. 74LVC1G79 Product data sheet 74LVC1G79 n.c. GND 001aaf189 Transparent top view Fig 5 ...

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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input CP ↑ ↑ HIGH voltage level LOW voltage level; ↑ = LOW-to-HIGH CP transition don’t care lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134) ...

Page 5

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC ΔI additional supply current CC C input capacitance I = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay see set-up time D to CP; see hold time D to CP; see pulse width CP HIGH or LOW; W see maximum CP; see max frequency 74LVC1G79 ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions C power dissipation capacitance V CC [1] Typical values are measured the same as t and PLH PHL [ used to determine the dynamic power dissipation (P PD × V × ...

Page 9

... NXP Semiconductors D input CP input Q output Measurement points are given in V and V are typical output voltage levels that occur with the output Fig 8. Clock (CP) to output (Q) propagation delay times, clock pulse width set-up times, the hold times and maximum clock pulse frequency Table 9 ...

Page 10

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 10. ...

Page 11

... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 10 ...

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... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions) UNIT 0.100 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT753 Fig 11. Package outline SOT753 (SC-74A) 74LVC1G79 Product data sheet scale 3.1 1.7 3.0 0.6 0.95 2.7 1.3 2 ...

Page 13

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 14

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13 ...

Page 15

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 16

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 17

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G79 v.8 20100930 • Modifications: Added type number 74LVC1G79GN (SOT1115/XSON6 package). • ...

Page 18

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 19

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC1G79 Product data sheet 16 ...

Page 20

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline ...

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