72V2113L7-5BCI Integrated Device Technology (Idt), 72V2113L7-5BCI Datasheet - Page 12

• Manufacturer Part Number: 72V2113L7-5BCI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 256K x 18/512K x 9 100-Pin CABGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V2113L7-5BCI

• Package: 100CABGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4.5 Mb
• Organization: 256Kx18|512Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by
the state of the FWFT/SI input.
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
on which timing mode is in effect.
IDT STANDARD MODE
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 65,537th word for the IDT72V2103 and 131,073rd
word for the IDT72V2113. If both x9 Input and x9 Output bus Widths are
selected, (D/2 + 1) = the 131,073rd word for the IDT72V2103 and 262,145th
word for the IDT72V2113. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or
x18 Output bus Width is selected, (D-m) = (131,072-m) writes for the IDT72V2103
and (262,144-m) writes for the IDT72V2113. If both x9 Input and x9 Output bus
Widths are selected, (D-m) = (262,144-m) writes for the IDT72V2103 and
(524,288-m) writes for the IDT72V2113. The offset “m” is the full offset value.
The default setting for these values are stated in the footnote of Table 2. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 131,072
writes for the IDT72V2103 and 262,144 writes for the IDT72V2113. If both x9
Input and x9 Output bus Widths are selected, D = 262,144 writes for the
IDT72V2103 and 524,288 writes for the IDT72V2113, respectively.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
The IDT72V2103/72V2113 support two different timing modes of opera-
Various signals, both input and output signals operate differently depending
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
n)
. It also uses Input Ready (IR) to indicate
n
after three RCLK rising
TM
NARROW BUS FIFO
TM
NARROW BUS FIFO
12
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
register-buffered outputs.
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
manner outlined in Table 4. To write data into the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
operations were taking place, the HF would toggle to LOW once the (D/2 + 2)
words were written into the FIFO. If x18 Input or x18 Output bus Width is selected,
(D/2 + 2) = the 65,538th word for the IDT72V2103 and 131,074th word for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
(D/2 + 2) = the 131,074th word for the IDT72V2103 and 262,146th word for
the IDT72V2113. Continuing to write data into the FIFO will cause the PAF to
go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes
to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (131,073-m)
writes for the IDT72V2103 and (262,145-m) writes for the IDT72V2113. If both
x9 Input and x9 Output bus Widths are selected, (D-m) = (262,145-m) writes
for the IDT72V2103 and (524,289-m) writes for the IDT72V2113. The offset
m is the full offset value. The default setting for these values are stated in the
footnote of Table 2.
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected,
D = 131,073 writes for the IDT72V2103 and 262,145 writes for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 writes for
the IDT72V2103 and 524,289 writes for the IDT72V2113, respectively. Note
that the additional word in FWFT mode is due to the capacity of the memory plus
output register.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n+1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
buffered, and the IR flag output is double register-buffered.
12.
If the FIFO is full, the first read operation will cause FF to go HIGH.
When configured in IDT Standard mode, the EF and FF outputs are double
Relevant timing diagrams for IDT Standard mode can be found in Figure
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
When configured in FWFT mode, the OR flag output is triple register-
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JUNE 1, 2010