72V2113L7-5BCI Integrated Device Technology (Idt), 72V2113L7-5BCI Datasheet - Page 2

• Manufacturer Part Number: 72V2113L7-5BCI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 256K x 18/512K x 9 100-Pin CABGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V2113L7-5BCI

• Package: 100CABGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4.5 Mb
• Organization: 256Kx18|512Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

DESCRIPTION:
First-In-First-Out (FIFO) memories with clocked read and write controls and a
flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improve-
ments over previous SuperSync FIFOs, including the following:
• Flexible x9/x18 Bus-Matching on both read and write ports.
• The limitation of the frequency of one clock input with respect to the other has
PIN CONFIGURATIONS
NOTE:
1. DNC = Do Not Connect.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
been removed. The Frequency Select pin (FS) has been removed, thus it
is no longer necessary to select which of the two clock inputs, RCLK or WCLK,
is running at the higher frequency.
The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS
INDEX
DNC
DNC
WEN
GND
SEN
GND
D17
D16
D15
D14
D13
D12
D11
D10
V
V
V
D9
D8
IW
CC
CC
CC
(1)
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TM
TQFP (PN80-1, order code: PF)
NARROW BUS FIFO
TM
TOP VIEW
NARROW BUS FIFO
2
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an
• Asynchronous/Synchronous translation on the read or write ports.
• High density offerings up to 4 Mbit.
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
Bus-Matching SuperSync FIFOs are particularly appropriate for network,
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COMMERCIAL AND INDUSTRIAL
6119 drw02
TEMPERATURE RANGES
V
V
RT
OE
Q17
Q16
GND
GND
Q15
Q14
Q13
Q12
GND
Q11
GND
Q10
Q9
Q8
Q7
V
CC
CC
CC
JUNE 1, 2010