72230L15TP Integrated Device Technology (Idt), 72230L15TP Datasheet - Page 6

• Manufacturer Part Number: 72230L15TP
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 8 28-Pin PDIP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72230L15TP

• Package: 28PDIP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 16 Kb
• Organization: 2Kx8
• Data Bus Width: 8 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
2. The Clocks (RCLK, WCLK) can be free-running during reset.
NOTE:
1. t
D
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
WCLK
Q
EF, AE
RCLK
FF, AF
0
WEN
REN
0
rising edge of WCLK is less than t
WEN
- D
SKEW1
REN
- Q
FF
RS
7
7
is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the
SKEW1
t
SKEW1
, then FF may not change state until the next WCLK edge.
(1)
t
CLKH
t
t
t
t
WFF
RSF
RSF
RSF
t
RS
t
t
RSS
RSS
t
DATA IN VALID
CLK
Figure 3. Write Cycle Timing
Figure 2. Reset Timing
t
CLKL
t
DS
t
ENS
6
t
t
DH
ENH
t
t
RSR
RSR
t
WFF
OE = 1
OE = 0
COMMERCIAL TEMPERATURE RANGE
(1)
NO OPERATION
JANUARY 8, 2009
2680 drw 05
2680 drw 04