72230L15TP Integrated Device Technology (Idt), 72230L15TP Datasheet - Page 7

• Manufacturer Part Number: 72230L15TP
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 8 28-Pin PDIP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72230L15TP

• Package: 28PDIP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 16 Kb
• Organization: 2Kx8
• Data Bus Width: 8 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. t
NOTE:
1. When t
Q
Q
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
D
WCLK
WCLK
RCLK
RCLK
0
0
0
WEN
WEN
REN
REN
rising edge of RCLK is less than t
When
The Latency Timing apply only at the Empty Boundary (EF = LOW).
- Q
- Q
SKEW1
- D
OE
OE
EF
EF
7
7
7
t
is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of WCLK and the
SKEW1
SKEW1
≥ minimum specification, t
< minimum specification, t
t
ENS
SKEW1
t
OLZ
t
DS
, then EF may not change state until the next RCLK edge.
FRL
t
FRL
ENH
t
ENS
maximum = 2t
maximum = t
t
CLKH
D0
t
REF
(first valid write)
t
t
A
SKEW1
t
CLK
OE
CLK
Figure 5. First Data Word Latency Timing
+ t
+ t
t
SKEW1
SKEW1
CLK
NO OPERATION
Figure 4. Read Cycle Timing
or t
t
CLK
t
OLZ
FRL
t
REF
+ t
(1)
t
SKEW1
CLKL
7
t
ENS
D1
t
OE
t
VALID DATA
SKEW1
t
(1)
A
t
REF
D2
COMMERCIAL TEMPERATURE RANGE
t
OHZ
D0
t
A
JANUARY 8, 2009
D3
D1
2680 drw 07
2680 drw 06