72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 22

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

TABLE 5 — I/O CONFIGURATION
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROM MARK OPERATION
starting at a user-selected position. The FIFO is first put into retransmit mode that
will ‘mark’ a beginning word and also set a pointer that will prevent ongoing FIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the ‘marked’ position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection over-
writing the previous mark location. Retransmit operation is available in both IDT
standard and FWFT modes.
to-High transition on RCLK when the ‘MARK’ input is HIGH and EF is HIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
the first retransmit data. The FIFO remains in retransmit mode until a rising edge
on RCLK occurs while MARK is LOW.
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled)
before bringing RT LOW. The device indicates the start of retransmit setup by
setting EF LOW, also preventing reads. When EF goes HIGH, retransmit setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first ‘marked’ word following a retransmit setup requires a LOW on REN (read
enabled).
functions, however write operations to the ‘marked’ location will be prevented.
See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant
timing diagram.
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WHSTL: HIGH = HSTL
Dn (I/P)
WCLK/WR (I/P)
WEN (I/P)
WCS (I/P)
The Retransmit from Mark feature allows FIFO data to be read repeatedly
During IDT standard mode the FIFO is put into retransmit mode by a Low-
Once a ‘marked’ location has been set (and the device is still in retransmit
Note, write operations may continue as normal during all retransmit
Parallel reading of the offset registers is always permitted regardless of
WHSTL SELECT
LOW = LVTTL
RCLK/RD (I/P)
RCS (I/P)
MARK (I/P)
REN (I/P)
OE (I/P)
RT (I/P)
Qn (O/P)
RHSTL: HIGH = HSTL
RHSTL SELECT
LOW = LVTTL
EF/OR (O/P)
PAF (O/P)
EREN (O/P)
PAE (O/P)
FF/IR (O/P)
HF (O/P)
ERCLK (O/P)
TDO (O/P)
22
SCLK (I/P)
LD (I/P)
MRS (I/P)
TCK (I/P)
TMS (I/P)
SEN (I/P)
FWFT/SI (I/P)
edge when the ‘MARK’ input is HIGH and OR is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
can be initiated by a rising RCLK edge while the retransmit input (RT) is LOW.
REN must be HIGH (reads disabled) before bringing RT LOW. The device
indicates the start of retransmit setup by setting OR HIGH.
RCLK edge after retransmit setup is complete, (RT goes HIGH), the contents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of REN, a
LOW on REN is not required for the first word. Reading all subsequent words
requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
72T1895 there must be a minimum of 32 bytes of data between the write pointer
and read pointer when the MARK is asserted, for the IDT72T18105/72T18115
there must be a minimum of 128 bytes and for the IDT72T18125 there must be
a minimum of 256 bytes. Remember, 2(x9) bytes = 1(x18) word. (32 bytes =
16 word = 8 long words). Also, once the MARK is set, the write pointer will not
increment past the “marked” location until the MARK is deasserted. This
prevents “overwriting” of retransmit data.
HSTL/LVTTL I/O
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
the power consumption (in stand-by mode by utilizing the WCS input).
and are purely device configuration pins.
SHSTL: HIGH = HSTL
Both the write port and read port are user selectable between HSTL or
Note, that when the write port is selected for HSTL mode, the user can reduce
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
Once a marked location has been set (and the device is still in retransmit
When OR goes LOW, retransmit setup is complete and on the next rising
Note, for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/
SHSTL SELECT
LOW = LVTTL
2Kx18/4Kx9, 4Kx18/
PRS (I/P)
TRST (I/P)
TDI (I/P)
COMMERCIAL AND INDUSTRIAL
IW (I/P)
BM (I/P)
ASYR (I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
TEMPERATURE RANGES
STATIC PINS
LVTTL ONLY
FEBRUARY 10, 2009
OW (I/P)
ASYW (I/P)
BE (I/P)
FSEL0 (I/P)
PFM (I/P)
WHSTL (I/P)