72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 6

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PROGRAMMABLE ALMOST-FULL (PAF)
I W
H
H
L
L
FULL FLAG/INPUT READY (FF/IR)
FIRST WORD FALL THROUGH/
WRITE CHIP SELECT (WCS)
WRITE CLOCK (WCLK/WR)
(x18, x9) DATA IN (D
SERIAL INPUT (FWFT/SI)
SERIAL CLOCK (SCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
Figure 1. Single Device Configuration Signal Flow Diagram
PARTIAL RESET (PRS)
INPUT WIDTH (IW)
LOAD (LD)
OW
0
H
H
L
L
- D
n
)
72T18105
72T18115
72T18125
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
IDT
6
MASTER RESET (MRS)
OUTPUT WIDTH (OW)
REN ECHO, EREN
RCLK ECHO, ERCLK
RETRANSMIT (RT)
PROGRAMMABLE ALMOST-EMPTY (PAE)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
EMPTY FLAG/OUTPUT READY (EF/OR)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
(x18, x9) DATA OUT (Q
MARK
OUTPUT ENABLE (OE)
READ CHIP SELECT (RCS)
Write Port Width
2Kx18/4Kx9, 4Kx18/
x18
x18
x9
x9
0
- Q
COMMERCIAL AND INDUSTRIAL
n
)
TEMPERATURE RANGES
Read Port Width
FEBRUARY 10, 2009
5909 drw03
x18
x18
x9
x9