72V245L15TFI Integrated Device Technology (Idt), 72V245L15TFI Datasheet - Page 22

• Manufacturer Part Number: 72V245L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 18 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V245L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 72 Kb
• Organization: 4Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
the application requirements are for 256/512/1,024/2,048/4,096 words or less.
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input Ready.
Because of variations in skew between RCLK and WCLK, it is possible for flag
assertion and deassertion to vary by one cycle between FIFOs. To avoid
problems the user must create composite flags by gating the Empty Flags/Output
Ready of every FIFO, and separately gating all Full Flags/Input Ready. Figure
NOTE:
1. Do not connect any output control signals directly together.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
A single IDT72V205/72V215/72V225/72V235/72V245 may be used when
Word width may be increased simply by connecting together the control
DATA IN (D)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
FULL FLAG/INPUT
READY (FF/IR)
WRITE CLOCK (WCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (D
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
36
0
- D
17
18
)
Figure 29. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
FF/IR
FL
RESET (RS)
72V205
72V215
72V225
72V235
72V245
WXI RXI
EF/OR
FL
18
72V205
72V215
72V225
72V235
72V245
IDT
RXI
22
These FIFOs are in a single Device Configuration when the First Load (FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
TM
29 demonstrates a 36-word width by using two IDT72V205/72V215/72V225/
72V235/72V245s. Any word width can be attained by adding additional
IDT72V205/72V215/72V225/72V235/72V245s. These FIFOs are in a single
Device Configuration when the First Load (FL), Write Expansion In (WXI) and
Read Expansion In (RXI) control inputs are configured as (FL, RXI,
WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure
29). Please see the Application Note AN-83.
RESET (RS)
18
WXI
FF/IR
FL
RESET (RS)
72V205
72V215
72V225
72V235
72V245
WXI RXI
EMPTY FLAG/OUTPUT READY (EF/OR)
EF/OR
18
PROGRAMMABLE (PAF)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
COMMERCIAL AND INDUSTRIAL
READ CLOCK (RCLK)
READ ENABLE (REN)
DATA OUT (Q
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT
READ CLOCK (RCLK)
READ ENABLE (REN)
DATA OUT (Q)
TEMPERATURE RANGES
READY (EF/OR)
OCTOBER 22, 2008
0
- Q
4294 drw 28
17
)
36
4294 drw 29