72V245L15TFI Integrated Device Technology (Idt), 72V245L15TFI Datasheet - Page 23

• Manufacturer Part Number: 72V245L15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 18 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V245L15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 72 Kb
• Organization: 4Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using three IDT72V205/72V215/72V225/72V235/72V245s.
Maximum depth is limited only by signal loading.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
WRITE ENABLE
These devices can easily be adapted to applications requiring more than
Follow these steps:
1. The first device must be designated by grounding the First Load (FL)
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to
WRITE CLOCK
control input.
the Write Expansion In (WXI) pin of the next device. See Figure 30.
DATA IN
RESET
LOAD
FF/IR
PAF
Figure 30. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
FIRST LOAD (FL)
Vcc
Vcc
WCLK
RS
Dn
FL
FF/IR
PAF
WCLK
WEN
RS
Dn
FL
FF/IR
PAF
WEN
LD
LD
WCLK
WEN
RS
Dn
FF/IR
PAF
LD
WXO
WXO
WXO
WXI
WXI
WXI
72V205
72V215
72V225
72V235
72V245
72V205
72V215
72V225
72V235
72V245
72V205
72V215
72V225
72V235
72V245
IDT
IDT
IDT
RXI
RXO
EF/OR
EF/OR
RXI
RXO
RXI
EF/OR
RXO
RCLK
RCLK
RCLK
REN
REN
PAE
PAE
REN
PAE
OE
OE
Qn
Qn
OE
Qn
23
TM
4. The Read Expansion Out (RXO) pin of each device must be tied to the
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in this Depth Expansion
7. EF, FF, PAE, and PAF are created with composite flags by ORing
8. In Daisy Chain mode, the flag outputs are single register-buffered and
Read Expansion In (RXI) pin of the next device. See Figure 30.
Configuration.
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
the partial flags are in asynchronous timing mode.
PAE
COMMERCIAL AND INDUSTRIAL
EF/OR
TEMPERATURE RANGES
OCTOBER 22, 2008
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA OUT
4294 drw 30