ZY7115HG-T2 POWER ONE, ZY7115HG-T2 Datasheet - Page 28

• Manufacturer Part Number: ZY7115HG-T2
• Description: Module DC-DC 1-OUT 0.5V to 5.5V 15A 25-Pin SMT T/R
• Manufacturer: POWER ONE

Specifications of ZY7115HG-T2

• Product: Non-Isolated / POL
• Input Voltage Range: 3 V to 13.2 V
• Number Of Outputs: 1
• Output Voltage (channel 1): 0.5 V to 5.5 V
• Output Current (channel 1): 15 A
• Package / Case Size: 8 mm x 32 mm x 14 mm
• Output Voltage: 0.5 V to 5.5 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Controller window or directly via the I
writing into the DCL register shown in Figure 54.
8.4.4
To speed up the PWM response in case of heavy
dynamic loads, the duty cycle can be forced either to
0 or the duty cycle limit depending on the polarity of
the transient. This function is equivalent to having
two comparators defining a window around the
output voltage setpoint.
inside the window, it will produce gradual duty cycle
change proportional to the error signal. If the error
signal goes outside the window (usually due to large
output current steps), the duty cycle will change to its
limit in one switching cycle. In most cases this will
significantly improve transient response of the
controller, reducing amount of required external
capacitance.
Under certain circumstances, usually when the
maximum duty cycle limit significantly exceeds its
nominal value, the ADC saturation can lead to the
overcompensation of the output error.
phenomenon manifests itself as low frequency
oscillations on the output of the POL. It can usually
be reduced or eliminated by disabling the ADC
saturation or limiting the maximum duty cycle to 120-
140% of the calculated value. It is not recommended
to use ADC saturation for output voltages higher
than 2.0V.
The
programmed in the GUI PWM Controller window or
directly via the I
register.
MDS-0006 Rev. 3.6, 02-Jul-10
Bit 7:2 DCL[5:0], Duty Cycle Limitation
Bit 1:
Bit 0:
R/W-1
DCL5
Bit 7
00h: 0
01h: 1/64
…
3Fh: 63/64
HI, ADC high saturation feed-forward
0: disabled
1: enabled
LO, ADC low saturation feed-forward
0: disabled
1: enabled
ADC
R/W-1
DCL4
ADC Saturation Feedforward
Figure 54. Duty Cycle Limit Register
saturation
R/W-1
DCL3
2
C bus by writing into the DCL
R/W-0
DCL2
When an error signal is
R/W-1
feedforward
DCL1
R/W-0
DCL0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
www.power-one.com
R/W-0
2
HI
C bus by
can
ZY7115 15A DC-DC Intelligent POL Data Sheet
R/W-0
Bit 0
LO
The
be
3V to 13.2V Input
8.4.5
Feedback loop compensation can be programmed in
the GUI PWM Controller window by setting
frequency of poles and zeros of the transfer function.
The transfer function of the POL converter is shown
in Figure 55. It is a third order function with two
zeros and three poles. Pole 1 is the integrator pole,
Pole 2 is used in conjunction with Zero 1 and Zero 2
to adjust the phase lead and limit the gain increase
in mid band. Pole 3 is used as a high frequency low-
pass filter to limit PWM noise.
Positions of poles and zeroes are determined by
coefficients of the digital filter.
characterized by four numerator coefficients (C
C
B
when desired frequency of poles and zeros is
entered in the GUI PWM Controller window. The
coefficients are stored in the C0H, C0L, C1H, C1L,
C2H, C2L, C3H, C3L, B1, B2, and B3 registers.
Note:
Programming feedback loop compensation allows
optimizing POL performance for various application
conditions. For example, increase in bandwidth can
significantly improve dynamic response.
Magnitude[dB]
2
3
).
, C
Phase
3
frequencies into the digital filter coefficients. It is strongly
recommended to use the GUI to determine the filter
coefficients.
The coefficients are automatically calculated
The
-135
-180
) and three denominator coefficients (B
+45
-45
-90
50
40
30
20
10
[°]
0
Feedback Loop Compensation
Figure 55. Transfer Function of PWM
GUI
0.1
0.1
automatically
1
1

Z1
0.5V to 5.5V Output
P1 Z2
transforms
10
10
P2
Page 28 of 34
100
100
P3
The filter is
zero
1000
1000
P1: Pole 1
P2: Pole 3
P3: Pole 3
Z1: Zero 1
Z2: Zero 2
and
1
0
, B
, C
[kHz]
[kHz]
Freq
Freq
pole
1
2
,
,