LC4064V-10TN100I LATTICE SEMICONDUCTOR, LC4064V-10TN100I Datasheet - Page 41

• Manufacturer Part Number: LC4064V-10TN100I
• Description: CPLD ispMACH® 4000V Family 64 Macro Cells 125MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC4064V-10TN100I

• Package: 100TQFP
• Family Name: ispMACH® 4000V
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 125 MHz
• Number Of Product Terms Per Macro: 80
• Memory Type: EEPROM
• Operating Temperature: -40 to 105 °C

Lattice Semiconductor
Switching Test Conditions
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 11.
Figure 12. Output Test Load, LVTTL and LVCMOS Standards
Table 11. Test Fixture Required Components
LVCMOS I/O, (L -> H, H -> L)
LVCMOS I/O (Z -> H)
LVCMOS I/O (Z -> L)
LVCMOS I/O (H -> Z)
LVCMOS I/O (L -> Z)
1. C
L
includes test fixtures and probe capacitance.
Test Condition
DUT
106 106
106
106
R


1
106
106
R


2
V
R 1
R 2
41
CCO
35pF
35pF
35pF
5pF
5pF
C
L
ispMACH 4000V/B/C/Z Family Data Sheet
1
C L
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = V
LVCMOS 1.8 = V
1.5V
1.5V
V
V
OH
OL
+ 0.3
- 0.3
0213A/ispm4k
Timing Ref.
Point
Test
CCO
CCO
/2
/2
LVCMOS 3.3 = 3.0V
LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
3.0V
3.0V
3.0V
3.0V
V
CCO