LCMXO2280C-3FTN256I LATTICE SEMICONDUCTOR, LCMXO2280C-3FTN256I Datasheet - Page 3
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LCMXO2280C-3FTN256I
Manufacturer Part Number
LCMXO2280C-3FTN256I
Description
CPLD MachXO Family 1140 Macro Cells 1.8V/2.5V/3.3V 256-Pin FTBGA Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LCMXO1200C-3FTN256I.pdf
(96 pages)
Specifications of LCMXO2280C-3FTN256I
Package
256FTBGA
Family Name
MachXO
Number Of Macro Cells
1140
Maximum Propagation Delay Time
5.1 ns
Number Of User I/os
211
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Ram Bits
28262.4
Memory Type
SRAM
Operating Temperature
-40 to 100 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2280C-3FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Introduction
Lattice Semiconductor
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
®
The ispLEVER
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
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