M4A5-128/64-10YNC LATTICE SEMICONDUCTOR, M4A5-128/64-10YNC Datasheet - Page 11

• Manufacturer Part Number: M4A5-128/64-10YNC
• Description: CPLD ispMACH™ 4A Family 5K Gates 128 Macro Cells 83.3MHz/118MHz EECMOS Technology 5V 100-Pin PQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4A5-128/64-10YNC

• Package: 100PQFP
• Family Name: ispMACH™ 4A
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 83.3|118 MHz
• Number Of Product Terms Per Macro: 20
• Operating Temperature: 0 to 70 °C

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
e. T-type with programmable T polarity
c. Latch with XOR
a. D-type with XOR
L
T
G
D
AP AR
AP AR
AP AR
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
Q
Q
Q
ispMACH 4A Family
b. D-type with programmable D polarity
d. Latch with programmable D polarity
f. Combinatorial with XOR
D
L
G
AP AR
AP AR
Q
Q
17466G-011
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