XC2C128-7CPG132I Xilinx Inc, XC2C128-7CPG132I Datasheet
XC2C128-7CPG132I
Specifications of XC2C128-7CPG132I
Available stocks
Related parts for XC2C128-7CPG132I
XC2C128-7CPG132I Summary of contents
Page 1
... The design features are supported starting with Xilinx ISE® 4.1i WebPACK tool. Additional details can be found in page 14. Table 1 shows the macrocell capacity and key timing parameters for the CoolRunner-II CPLD family. XC2C64A XC2C128 XC2C256 64 128 64 100 4.6 5.7 2.0 2 ...
Page 2
... VQ100 (100-pin 1.0mm QFP), TQ144 (144-pin 1.4mm QFP), and FT256 (256-ball 1.0mm spacing FLBGA). The FT256 is particularly important for slim dimensioned porta- ble products with mid- to high-density logic requirements. XC2C128 XC2C256 XC2C384 - - ...
Page 3
... Design changes are easily and automatically managed by the software, which exploits the 100% routability of the Programmable Logic Array within each FB. This extremely robust building block delivers the DS090 (v3.1) September 11, 2008 Product Specification for a summary of XC2C64A XC2C128 XC2C256 ✓ ✓ ✓ ✓ ...
Page 4
CoolRunner-II CPLD Family path. The BSC and ISP block has the JTAG controller and In-System Programming Circuits. MC1 I/O Pin MC2 I/O Pin 16 MC16 I/O Pin 16 JTAG BSC and ISP Function Block The CoolRunner-II CPLD FBs contain 16 ...
Page 5
R Macrocell The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum of product (SOP) logic expressions that comprise inputs and span 56 product terms within a single function block. The ...
Page 6
CoolRunner-II CPLD Family software. The AIM minimizes both propagation delay and power as it makes attachments to the various FBs. I/O Block I/O blocks are primarily transceivers. However, each I/O is either automatically compliant with standard voltage ranges or can ...
Page 7
... CPLDs are widely used as voltage interface translators. To that end, the output pins are grouped in large banks. The XC2C32A, XC2C64A, XC2C128 and XC2C256 devices support two output banks. With two, the outputs switch to one of two selected output voltage levels, unless both banks are set to the same voltage ...
Page 8
CoolRunner-II CPLD Family nally generated DataGATE control logic can be assigned to this I/O pin with the BUFG=DATA_GATE attribute. Latch Latch Figure 6: DataGATE Architecture (output drivers not shown) Global Signals Global signals, clocks (GCK), sets/resets (GSR), and output enables ...
Page 9
R Additional Clock Options: Division, DualEDGE, and CoolCLOCK Clock Divider A clock divider circuit has been included in the CoolRunner-II CPLD architecture to divide one externally supplied global clock by standard values. The allowable val- ues for the division are ...
Page 10
CoolRunner-II CPLD Family CLK_CT PTC Figure 9: Macrocell Clock Chain with DualEDGE Option Shown GCK2 Synch Reset Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option Design Security Designs can be secured during programming to prevent either accidental ...
Page 11
R Timing Model Figure 11 shows the CoolRunner-II CPLD timing model. It represents one aspect of the overall architecture from a tim- ing viewpoint. Each little block is a time delay that a signal incurs if the signal passes through ...
Page 12
CoolRunner-II CPLD Family Programming The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development JTAG-compatible board tester simple microprocessor interface that emulates the JTAG instruction ...
Page 13
programmed at any time. All devices are shipped in the erased state from the factory. Applying power to a blank part might result in a higher cur- rent flow as the part initializes. This behavior is normal ...
Page 14
CoolRunner-II CPLD Family Absolute Maximum Ratings Symbol (2) V Supply voltage relative to GND CC (3) V Input voltage relative to GND I T Ambient Temperature (C-grade) A Ambient Temperature (I-grade) (4) T Maximum junction temperature J T Storage temperature ...
Page 15
... Family Data Sheet) s090.pdf http://www.xilinx.com/support/documentation/data_sheets/d (XC2C32A Data Sheet) s310.pdf http://www.xilinx.com/support/documentation/data_sheets/d (XC2C64A Data Sheet) s311.pdf http://www.xilinx.com/support/documentation/data_sheets/d (XC2C128 Data Sheet) s093.pdf http://www.xilinx.com/support/documentation/data_sheets/d (XC2C256 Data Sheet) s094.pdf http://www.xilinx.com/support/documentation/data_sh eets/ds095.pdf (XC2C384 Data Sheet) http://www.xilinx.com/support/documentation/data_sheets/d (XC2C512 Data Sheet) s096 ...
Page 16
... Add link to power estimation appnote, page 14. 09/11/08 3.1 Removed reference to XC2C32 and XC2C64 devices. See Product Discontinuation Notice xcn05017.pdf Removed references to PC44 and PCG44 packages. See Product Discontinuation Notice xcn07022.pdf 16 Revision for XC2C128. SYSTEM1 . . www.xilinx.com before V power CCINT CCIO DS090 (v3.1) September 11, 2008 ...