XC2C256-6VQG100C Xilinx Inc, XC2C256-6VQG100C Datasheet - Page 23
![CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 256MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC2C256-6VQG100C
Manufacturer Part Number
XC2C256-6VQG100C
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 256MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C256-6VQG100C
Package
100VTQFP
Family Name
CoolRunnerÂ-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
6 ns
Number Of User I/os
80
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
256 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.7ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
80
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C256-6VQG100C
Manufacturer:
XILINX
Quantity:
670
Additional Information
Additional information is available for the following CoolRunner-II topics:
•
•
•
•
•
•
•
Revision History
The following table shows the revision history for this document.
DS094 (v3.2) March 8, 2007
Product Specification
05/09/02
05/13/02
10/31/02
03/17/03
04/02/03
01/26/04
02/26/04
08/03/04
08/19/04
10/01/04
03/07/05
06/28/05
03/20/06
02/15/07
03/08/07
5/20/06
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
XAPP376: Logic Engine
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
XAPP399: Assigning VREF Pins
Date
R
Version
1.0
1.1
1.2
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
Initial Xilinx release.
Updated AC Electrical Characteristics and added new parameters.
Corrected package user I/O, added Voltage Referenced DC tables.
Added Characterization numbers for product release and device part marking
Updated T
Updated Device Part Marking. Updated links and Tsol.
Corrected Theta JC value on XC2C256-7TQ144.
Pb-free documentation
Changes to I
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
Removed -5 speed grade. Changes to Table 1, I/O Standards.
Move to Product Specification. Change to T
grade.
Add Warranty Disclaimer. Add note to Pin Description table that
be used for general purpose I/O.
Moved T
Corrections to timing parameters t
t
for the -7 speed grade. Values now match the software. There were no changes to silicon
or characterization. Change to V
Fixed typo in note for V
SUEC
, t
CW
CONFIG
, t
SOL
CDRSU
CCSB
max from 260 to 220. Changed I
specification values from MIN column to MAX column, page 7.
maximum specifications in DC Electrical Characteristics table, on page 3.
, and f
www.xilinx.com
IL
TOGGLE
for LVCMOS18; removed note for V
To access these and all application notes with their associ-
ated reference designs, click the following link and scroll
down the page until you find the document you want:
CoolRunner-II Data Sheets and Application Notes
Device Packages
IH
for -6 speed grade. Corrections to t
AOI
specification for 2.5V and 1.8V LVCMOS.
, t
PSUD
Revision
IN25
, t
PSU1
CCSB
, T
OUT25
, t
PSU2
units from mA to μA.
, T
, t
IN33
XC2C256 CoolRunner-II CPLD
PHD
IL
, and T
, t
for LVCMOS33.
GTS, GSR and GCK pins can
PCO
PSUD
, t
OUT33
POE
, t
CW
, t
for -7 speed
PAO
, and t
, t
AO
CDRSU
,
23