XC2C64A-5CP56C Xilinx Inc, XC2C64A-5CP56C Datasheet - Page 2

• Manufacturer Part Number: XC2C64A-5CP56C
• Description: CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 263MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC2C64A-5CP56C

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 1500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 5 ns
• Number Of User I/os: 45
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 263 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C

XC2C64A CoolRunner-II CPLD
RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
0.017
0
15
10
20
5
0
0
Table 1
1.8
25
A
for I/O stan-
Figure 1: I
50
= 25°C)
3.7
50
www.xilinx.com
(1)
100
5.5
75
CC
vs Frequency
Frequency (MHz)
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64A
1.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
IOSTANDARD
7.48
100
Attribute
150
Frequency (MHz)
LVCMOS15 requires Schmitt-trigger inputs.
11.0
150
(1)
200
Output
DS092_01_092302
V
3.3
3.3
2.5
1.8
1.5
CCIO
12.7
175
250
V
Input
DS311 (v2.3) November 19, 2008
CCIO
3.3
3.3
2.5
1.8
1.5
14.6
200
Input
V
N/A
N/A
N/A
N/A
N/A
Product Specification
REF
15.3
225
Termination
Voltage V
Board
N/A
N/A
N/A
N/A
N/A
17.77
240
T
R