XC2C64A-7CP56I Xilinx Inc, XC2C64A-7CP56I Datasheet

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XC2C64A-7CP56I

Manufacturer Part Number
XC2C64A-7CP56I
Description
CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2C64A-7CP56I

Package
56CSBGA
Family Name
CoolRunner™-II
Device System Gates
1500
Number Of Macro Cells
64
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
45
Number Of Logic Blocks/elements
4
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
159 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
-40 to 85 °C

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0
DS311 (v2.3) November 19, 2008
Features
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
DS311 (v2.3) November 19, 2008
Product Specification
Optimized for 1.8V systems
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Industry’s best 0.18 micron CMOS CPLD
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Available in multiple package options
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Advanced system features
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As fast as 4.6 ns pin-to-pin logic delays
As low as 15 μA quiescent current
Optimized architecture for effective logic synthesis
Multi-voltage I/O operation — 1.5V to 3.3V
44-pin VQFP with 33 user I/Os
48-land QFN with 37 user I/Os
56-ball CP BGA with 45 user I/Os
100-pin VQFP with 64 user I/Os
Pb-free available for all packages
Fastest in system programming
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IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Two separate I/O banks
RealDigital 100% CMOS product term generation
Flexible clocking modes
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Global signal options with macrocell control
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Efficient control term clocks, output enables, and
set/resets for each macrocell and shared across
function blocks
Advanced design security
Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
Open-drain output option for Wired-OR and LED
drive
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
PLA architecture
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Hot pluggable
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
1.8V ISP using IEEE 1532 (JTAG) interface
Optional DualEDGE triggered registers
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
Superior pinout retention
100% product term routability across function
block
R
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www.xilinx.com
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XC2C64A CoolRunner-II CPLD
Product Specification
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved.
This device consists of four Function Blocks inter-connected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 64A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
Table
1). This device is also 1.5V I/O com-
1

Related parts for XC2C64A-7CP56I

XC2C64A-7CP56I Summary of contents

Page 1

... Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS311 (v2.3) November 19, 2008 Product Specification 0 XC2C64A CoolRunner-II CPLD Product Specification 0 0 Description The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications ...

Page 2

... Resetable binary counter (one counter per function block). 2 LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica- tions. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C64A IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 ...

Page 3

... CCIO V = 1.9V 3.6V CC CCIO MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO V www.xilinx.com XC2C64A CoolRunner-II CPLD Value Units –0.5 to 2.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –65 to +150 °C +150 °C Min Max Units 1.7 1 ...

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... XC2C64A CoolRunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter ...

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... DS311 (v2.3) November 19, 2008 Product Specification (1) Test Conditions - - - I = –8 mA CCIO I = –0.1 mA CCIO mA CCIO I = 0.1 mA CCIO Test Conditions - - - www.xilinx.com XC2C64A CoolRunner-II CPLD Min. Max. 1.4 1 CCIO 0 0 CCIO = 1.4V V – 0.45 - CCIO = 1.4V V – 0.2 - CCIO = 1.4V - 0.4 = 1.4V - 0.2 Min. ...

Page 6

... XC2C64A CoolRunner-II CPLD AC Electrical Characteristics Over Recommended Operating Conditions Symbol T Propagation delay single p-term PD1 T Propagation delay OR array PD2 T Direct input register clock setup time SUD T Setup time (single p-term) SU1 T Setup time (OR array) SU2 T Direct input register hold time HD T P-term hold time ...

Page 7

... Output slew rate adder SLEW DS311 (v2.3) November 19, 2008 Product Specification -5 (1) Min. Max 1.4 0.0 0 www.xilinx.com XC2C64A CoolRunner-II CPLD -7 Min. Max. Units 1.7 - 2.4 2.6 - 4.0 1.6 - 2.5 2.4 - 3.5 2.7 - 3.9 1.9 - 2.8 5.3 - 6.1 2.0 - 2.5 0.5 - 0.8 0.4 - 0.8 ...

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... XC2C64A CoolRunner-II CPLD Internal Timing Parameters (Continued) Symbol Parameter I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder IN25 T Hysteresis input adder HYS25 T Output adder OUT25 T Output slew rate adder SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder ...

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... Number of Outputs Switching Figure 2: Derating Curve for T AC Test Circuit Figure 3: AC Load Circuit DS311 (v2.3) November 19, 2008 Product Specification Typical I/O Output Curves DS092_02_092302 PD www.xilinx.com XC2C64A CoolRunner-II CPLD Vo Output Volts Figure 4: Typical I/O Output Curves Vdde1 1.5V 1.8V 2.5V 3.3V 9 ...

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... XC2C64A CoolRunner-II CPLD Pin Descriptions Function Block Macrocell 1(GTS1) 9 1(GTS0) 10 1(GTS3) 11 1(GTS2) 12 1(GSR 2(GCK0) 7 2(GCK1 2(GCK2 (1) PC44 VQ44 QFG48 www.xilinx.com CP56 VQ100 I/O Banking F1 13 Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank 2 ...

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... XC2C64A CoolRunner-II CPLD CP56 VQ100 I/O Banking C4 91 Bank Bank Bank Bank Bank Bank Bank Bank Bank 2 A10 72 Bank 2 B10 71 Bank 2 C10 70 Bank Bank Bank 2 D10 64 Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank 1 H10 52 Bank 1 ...

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... Spacing XC2C64A-5QFG48C 0.5mm XC2C64A-7QFG48C 0.5mm XC2C64A-5VQ44C 0.8mm XC2C64A-7VQ44C 0.8mm XC2C64A-5CP56C 0.5mm XC2C64A-7CP56C 0.5mm XC2C64A-5VQ100C 0.5mm XC2C64A-7VQ100C 0.5mm XC2C64A-5VQG44C 0.8mm XC2C64A-7VQG44C 0.8mm XC2C64A-5CPG56C 0.5mm XC2C64A-7CPG56C 0.5mm XC2C64A-5VQG100C 0.5mm XC2C64A-7VQG100C 0.5mm XC2C64A-7VQ44I 0.8mm XC2C64A-7QFG48I 0.5mm XC2C64A-7CP56I 0.5mm XC2C64A-7VQ100I 0.5mm 12 (1) PC44 VQ44 QFG48 ...

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... Part marking for non-chip scale package Figure 5: Sample Package with Part Marking 4. Device code, speed, operating temperature, three digits not related to device part number. Device codes CP56 CPG56 QFG48. www.xilinx.com XC2C64A CoolRunner-II CPLD Package Body Comm(C) Dimensions I/O Ind. (I) 10mm x 10mm ...

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... XC2C64A CoolRunner-II CPLD Package Pinout Diagrams I/O (2) 1 I/O 2 I/O 3 GND 4 VQ44 I/O 5 I/O 6 Top View V 7 CCIO1 I/O 8 TDI 9 TMS 10 TCK 11 Figure 6: VQ44 Package I/O (2) 7 I/O 8 I/O 9 GND 10 PC44 I/O 11 I/O 12 Top View V 13 CCIO1 I TDI 16 TMS 17 TCK (1) - Global Output Enable ...

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... AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS311 (v2.3) November 19, 2008 Product Specification VQ100 Top View Figure 12: VQ100 Package www.xilinx.com XC2C64A CoolRunner-II CPLD I I/O 72 ...

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... XC2C64A CoolRunner-II CPLD Additional Information Additional information is available for the following CoolRunner-II CPLD topics at www.xilinx.com/support/documentation/coolrunner-ii.htm • Device pinouts in the density specific data sheets • Termination, power sequencing, voltage thresholds, and slew rate data in the CPLD IO User Guide Revision History The following table shows the revision history for this document. ...

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