XC2C64A-7CP56I Xilinx Inc, XC2C64A-7CP56I Datasheet - Page 11

• Manufacturer Part Number: XC2C64A-7CP56I
• Description: CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC2C64A-7CP56I

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 1500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 45
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 159 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: -40 to 85 °C

Pin Descriptions (Continued)
DS311 (v2.3) November 19, 2008
Product Specification
1.
2.
3.
This is an obsolete package type. It remains here for legacy support only.
GTS = global output enable, GSR = global set reset, GCK = global clock.
GCK, GSR, and GTS pins can also be used for general purpose I/Os.
Function Block
R
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Macrocell
10
11
12
13
14
15
16
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
PC44
35
34
33
29
28
27
26
25
24
12
14
18
19
20
22
11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(1)
www.xilinx.com
VQ44
29
28
27
23
22
21
20
19
18
12
13
14
16
5
6
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
QFG48
45
44
43
39
38
37
36
35
34
33
32
17
18
20
24
25
26
27
28
30
CP56
C10
D10
H10
G10
A10
B10
F10
E10
C4
A4
C5
A7
C8
A8
A9
A5
D8
E8
K6
H5
K7
H7
H8
K8
-
-
-
-
-
-
-
-
XC2C64A CoolRunner-II CPLD
VQ100
91
90
89
81
79
78
77
76
74
72
71
70
68
67
64
61
35
36
37
39
40
41
42
43
49
50
52
53
55
56
58
60
I/O Banking
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
11