XC95144-15TQG100C Xilinx Inc, XC95144-15TQG100C Datasheet - Page 4

• Manufacturer Part Number: XC95144-15TQG100C
• Description: CPLD XC9500 Family 3.2K Gates 144 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95144-15TQG100C

• Package: 100TQFP
• Family Name: XC9500
• Device System Gates: 3200
• Number Of Macro Cells: 144
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 144
• Number Of Gates: 3200
• Number Of I /o: 81
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1427

AC Characteristics
DS067 (v5.7) May 28, 2009
Product Specification
Notes:
1.
2.
Device Output
f
SYSTEM
Symbol
T
f
f
f
f
CNT
T
T
T
APRPW
T
T
CNT
CNT
SYSTEM
T
T
T
T
T
T
T
PCO
POD
WLH
PSU
POE
OD
PD
SU
CO
PH
OE
H
(1)
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
is also the Export Control Maximum flip-flop toggle rate, f
(2)
R
is the internal operating frequency for general purpose system designs spanning multiple FBs.
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width
(High or Low)
V
TEST
R
R
1
2
Parameter
C
L
Figure 3: AC Load Circuit
Output Type
www.xilinx.com
TOG
125.0
83.3
Min
4.5
0.5
4.0
4.0
7.0
XC95144-7
.
0
-
-
-
-
-
-
-
V
5.0V
3.3V
CCIO
Max
7.5
4.5
8.5
5.5
5.5
9.5
9.5
-
-
-
-
-
-
-
-
XC95144 In-System Programmable CPLD
V
111.1
5.0V
3.3V
66.7
XC95144-10
Min
TEST
6.0
2.0
4.0
4.5
7.5
0
-
-
-
-
-
-
-
Max
10.0
10.0
10.0
10.0
6.0
6.0
6.0
-
-
-
-
-
-
-
-
160Ω
260Ω
R
1
95.2
55.6
Min
XC95144-15
8.0
4.0
4.0
5.5
8.0
0
-
-
-
-
-
-
-
360Ω
120Ω
R
2
Max
15.0
12.0
11.0
11.0
14.0
14.0
8.0
-
-
-
-
-
-
-
-
DS067_03_110101
35 pF
35 pF
Units
C
MHz
MHz
L
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4