XC95144-15TQG100C Xilinx Inc, XC95144-15TQG100C Datasheet - Page 5

• Manufacturer Part Number: XC95144-15TQG100C
• Description: CPLD XC9500 Family 3.2K Gates 144 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95144-15TQG100C

• Package: 100TQFP
• Family Name: XC9500
• Device System Gates: 3200
• Number Of Macro Cells: 144
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 144
• Number Of Gates: 3200
• Number Of I /o: 81
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1427

Internal Timing Parameters
DS067 (v5.7) May 28, 2009
Product Specification
Notes:
1.
Symbol
Buffer Delays
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
T
T
T
T
T
T
T
T
T
T
T
LOGILP
T
T
T
T
T
PTA
T
SLEW
PTCK
PTSR
T
T
PTTS
T
LOGI
GCK
GSR
GTS
OUT
T
COI
AOI
PDI
SUI
RAI
T
EN
LF
IN
HI
F
PTA
(1)
is multiplied by the span of the function as defined in the XC9500 family data sheet.
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
FastCONNECT feedback delay
Function block local feedback delay
Incremental product term allocator delay
Slew-rate limited delay
R
Parameter
www.xilinx.com
Min
1.5
3.0
7.5
XC95144-7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
10.0
2.5
1.5
4.5
5.5
2.5
3.0
2.0
4.5
0.5
0.5
6.5
2.0
8.0
4.0
1.0
4.0
0
-
-
-
10.0
Min
XC95144 In-System Programmable CPLD
XC95144-10
2.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
11.0
3.5
2.5
6.0
6.0
3.0
3.0
2.5
3.5
1.0
0.5
7.0
2.5
3.5
1.0
4.5
9.5
0
-
-
-
10.0
Min
XC95144-15
3.5
4.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
11.5
11.0
11.0
4.5
3.0
7.5
4.5
2.5
3.0
5.0
3.0
0.5
8.0
3.0
3.5
1.0
5.0
0
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5