XC2S50E-6TQ144C Xilinx Inc, XC2S50E-6TQ144C Datasheet - Page 46
![FPGA Spartan®-IIE Family 50K Gates 1728 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC2S50E-6TQ144C
Manufacturer Part Number
XC2S50E-6TQ144C
Description
FPGA Spartan®-IIE Family 50K Gates 1728 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S50E-6TQ144C
Package
144TQFP
Family Name
Spartan®-IIE
Device Logic Cells
1728
Device Logic Units
384
Device System Gates
50000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
102
Ram Bits
32768
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
32768
Number Of I /o
102
Number Of Gates
50000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2S50E-6TQ144C
Manufacturer:
XILINX
Quantity:
1 450
Company:
Part Number:
XC2S50E-6TQ144C
Manufacturer:
XILINX
Quantity:
150
Part Number:
XC2S50E-6TQ144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
46
Combinatorial Delays
Multiplier Operation
Setup/Hold Times with Respect to Clock CLK
T
T
CCKX
CCKY
T
T
T
T
T
T
T
Symbol
T
T
T
T
T
T
T
GANDCY
FANDCY
GANDYB
T
T
FANDXB
FANDYB
T
T
OPGYB
OPCYG
OPCYF
T
CINXB
CINYB
OPXB
OPYB
OPGY
BXCY
CINX
CINY
OPX
OPY
BYP
/ T
/ T
CKCX
CKCY
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
CIN input to Y via XOR
CIN input to YB
CIN input to COUT output
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
CIN input to FFX
CIN input to FFY
Description
www.xilinx.com
1.2 / 0
1.2 / 0
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max
0.51
0.07
0.14
0.35
0.8
0.8
1.4
1.1
0.9
0.8
1.2
0.9
0.6
0.7
0.4
0.7
0.5
0.6
0.3
Speed Grade
-
-
1.3 / 0
1.3 / 0
Min
DS077-3 (v2.3) June 18, 2008
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
Product Specification
Max
0.15
0.8
0.9
1.5
1.3
1.0
0.9
1.3
1.0
0.6
0.7
0.1
0.7
0.5
0.4
0.8
0.6
0.7
0.4
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R