XC2VP7-5FFG672C Xilinx Inc, XC2VP7-5FFG672C Datasheet - Page 115
![FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA](/photos/6/74/67431/xc2vp7-5ffg672c_sml.jpg)
XC2VP7-5FFG672C
Manufacturer Part Number
XC2VP7-5FFG672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP7-5FFG672C
Package
672FCBGA
Family Name
Virtex-II ProÂ
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008
Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1370
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2VP7-5FFG672C
Manufacturer:
XILINX
Quantity:
745
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Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
,
Table 53: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVCMOS25
Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in
Characteristics Standard Adjustments,
page
Full Delay
Global Clock and IFF without DCM
relative to the Global Clock input signal with the slowest route and heaviest load.
if a “0” is listed, there is no positive hold time.
23.
IOB Input Switching
R
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
PSFD
Symbol
/T
PHFD
www.xilinx.com
XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
1.80/–0.44
1.82/–0.53
1.80/–0.34
1.76/–0.24
1.76/–0.24
1.75/–0.22
2.25/–0.54
2.93/–1.02
2.79/–0.72
2.79/–0.72
N/A
-7
Speed Grade
1.85/–0.41
1.83/–0.31
1.81/–0.24
1.83/–0.17
1.92/–0.26
2.40/–0.56
2.98/–0.93
2.79/–0.55
5.58/–2.35
1.83/–0.17
2.79/–0.55
-6
1.96/–0.43
1.90/–0.29
1.88/–0.19
1.92/–0.15
1.92/–0.15
1.99/–0.23
2.49/–0.54
3.00/–0.83
2.78/–0.41
2.78/–0.41
5.60/–2.35
-5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
44
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