XC2VP7-5FG456I Xilinx Inc, XC2VP7-5FG456I Datasheet - Page 95

• Manufacturer Part Number: XC2VP7-5FG456I
• Description: FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-II Pror

Specifications of XC2VP7-5FG456I

• Package: 456FBGA
• Family Name: Virtex-II Pro™
• Device Logic Units: 11088
• Number Of Registers: 9856
• Maximum Internal Frequency: 1050 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 248
• Ram Bits: 811008
• Number Of Logic Elements/cells: 11088
• Number Of Labs/clbs: 1232
• Total Ram Bits: 811008
• Number Of I /o: 248
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 33: IOB Input Switching Characteristics Standard Adjustments (Continued)
DS083 (v4.7) November 5, 2007
Product Specification
HSLVDCI, 1.8V
HSLVDCI, 2.5V
HSLVDCI, 3.3V
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL, Class III, with DCI
HSTL, Class IV, with DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
LVDS, 2.5V, with DCI
LVDSEXT, 2.5V, with DCI
LVDS, 2.5V, with Differential Termination (DT)
LVDSEXT, 2.5V, with DT
ULVDS, 2.5V, with DT
LDT, 2.5V, with DT
R
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
LVDSEXT_25_DCI
HSTL_IV_DCI_18
LVDSEXT_25_DT
HSTL_III_DCI_18
HSTL_II_DCI_18
IOSTANDARD
HSTL_I_DCI_18
SSTL18_II_DCI
ULVDS_25_DT
SSTL18_I_DCI
HSTL_IV_DCI
SSTL2_II_DCI
LVDS_25_DCI
HSTL_III_DCI
SSTL2_I_DCI
LVDS_25_DT
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_II_DCI
HSTL_I_DCI
LDT_25_DT
GTLP_DCI
Attribute
GTL_DCI
T
T
T
T
T
T
T
T
ILVDSEXT_25_DCI
T
IHSTL_III_DCI_18
IHSTL_IV_DCI_18
T
T
ILVDSEXT_25_DT
T
T
T
IHSTL_II_DCI_18
T
T
T
T
T
IHSTL_I_DCI_18
Parameter
T
ISSTL18_II_DCI
T
ISSTL18_I_DCI
IULVDS_25_DT
T
ISSTL2_II_DCI
ILVDS_25_DCI
IHSTL_III_DCI
IHSTL_IV_DCI
ISSTL2_I_DCI
ILVDS_25_DT
IHSLVDCI_18
IHSLVDCI_25
IHSLVDCI_33
IHSTL_II_DCI
T
IHSTL_I_DCI
ILDT_25_DT
Timing
IGTLP_DCI
IGTL_DCI
0.59
0.59
0.59
0.49
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.27
0.62
0.64
0.17
0.17
0.31
0.33
0.31
0.33
0.31
0.31
-7
Speed Grade
0.68
0.68
0.68
0.57
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.72
0.73
0.20
0.20
0.36
0.37
0.36
0.37
0.36
0.36
-6
0.75
0.75
0.75
0.62
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.79
0.81
0.22
0.22
0.40
0.41
0.40
0.41
0.40
0.40
-5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24