XC3S1600E-4FGG484I Xilinx Inc, XC3S1600E-4FGG484I Datasheet - Page 127

• Manufacturer Part Number: XC3S1600E-4FGG484I
• Description: FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S1600E-4FGG484I

• Package: 484FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 33192
• Device Logic Units: 3688
• Device System Gates: 1600000
• Number Of Registers: 29504
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 376
• Ram Bits: 663552
• Number Of Logic Elements/cells: 33192
• Number Of Labs/clbs: 3688
• Total Ram Bits: 663552
• Number Of I /o: 376
• Number Of Gates: 1600000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O Timing
Table 86: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
4.
Clock-to-Output Times
T
Symbol
ICKOFDCM
T
The numbers in this table are tested using the methodology presented in
Table 77
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
DCM output jitter is included in all measurements.
For minimums, use the values reported by the Xilinx timing analyzer.
ICKOF
R
and
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global Clock
pin to data appearing at the Output
pin. The DCM is used.
When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing at
the Output pin. The DCM is not used.
Table
80.
Table
Description
91. If the latter is true, add the appropriate Output adjustment from
www.xilinx.com
LVCMOS25
12 mA output drive,
Fast slew rate,
with DCM
LVCMOS25
12 mA output drive,
Fast slew rate,
without DCM
Conditions
(3)
Table 95
(2)
(2)
,
,
and are based on the operating conditions set forth in
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Device
Table
DC and Switching Characteristics
94.
Max
2.66
3.00
3.01
3.01
3.00
5.60
4.91
4.98
5.36
5.45
Speed Grade
-5
Max
2.79
3.45
3.46
3.46
3.45
5.92
5.43
5.51
5.94
6.05
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
127