XC3S1600E-4FGG484I Xilinx Inc, XC3S1600E-4FGG484I Datasheet - Page 185
![FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S1600E-4FGG484I
Manufacturer Part Number
XC3S1600E-4FGG484I
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FGG484I
Package
484FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
376
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
376
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
140
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
250
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
Double arrows (
between the XC3S100E and XC3S250E.
DS312-4 (v3.8) August 26, 2009
Product Specification
20
21
2
0
I/O: Unrestricted,
general-purpose user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated
configuration pins
N.C.: Not connected
IO_L02N_3/VREF_3
IO_L04N_3/LHCLK1
IO_L06N_3/LHCLK5
IO_L07N_3/LHCLK7
IO_L04P_3/LHCLK0
IO_L05P_3/LHCLK2
IO_L05N_3/LHCLK3
IO_L07P_3/LHCLK6
IO_L06P_3/LHCLK4
R
(
) IO/VREF_3 31
IO_L01P_3
IO_L01N_3
IO_L02P_3
IO_L03P_3
IO_L03N_3
IO_L08P_3 25
IO_L08N_3 26
IO_L09P_3 32
IO_L09N_3 33
IO_L10P_3 34
IO_L10N_3 35
IP/VREF_3 12
PROG_B
VCCAUX 30
VCCO_3 13
VCCO_3 28
(
(
VCCINT
GND
GND
GND
) indicates a pinout migration difference
) IP 10
) IP 29
IP
IP 18
IP 24
IP 36
11
14
15
16
17
19
20
21
22
23
27
1
2
3
4
5
6
7
8
9
Figure 83: TQ144 Package Footprint (top view)
42
16
13
4
DUAL: Configuration pin, then
possible user I/O
CLK: User I/O, input, or global
buffer input
JTAG: Dedicated JTAG port
pins
GND: Ground
www.xilinx.com
Bank 0
Bank 2
9
9
4
4
VREF: User I/O or input
voltage reference for bank
VCCO: Output voltage supply
for bank
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage (+2.5V)
108
107 IP
106 IO_L10N_1/LDC2
105 IO_L10P_1/LDC1
104 IO_L09N_1/LDC0
103 IO_L09P_1/HDC
102 VCCAUX
101 IP
100 VCCO_1
99
98 IO/A0
97 IO_L08N_1/A1
96 IO_L08P_1/A2
95 IP/VREF_1
94
93
92
91
90
89 IP
88
87
86
85
84 IP
83 IO/VREF_1
82 IO_L03N_1/A11
81 IO_L03P_1/A12
80
79 VCCO_1
78 IP
77 IO_L02N_1/A13
76 IO_L02P_1/A14
75 IO_L01N_1/A15
74 IO_L01P_1/A16
73
TMS
GND
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4
GND
IO_L05N_1/A7/RHCLK3
IO_L05P_1/A8/RHCLK2
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
VCCINT
GND
DS312-4_01_082009
Pinout Descriptions
185