XC3S400-4FTG256C Xilinx Inc, XC3S400-4FTG256C Datasheet - Page 73
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XC3S400-4FTG256C
Manufacturer Part Number
XC3S400-4FTG256C
Description
FPGA Spartan®-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S400-4FTG256C
Package
256FTBGA
Family Name
Spartan®-3
Device Logic Units
8064
Device System Gates
400000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
173
Ram Bits
294912
Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Total Ram Bits
294912
Number Of I /o
173
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Dc
0837
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1342
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S400-4FTG256C
Manufacturer:
XILINX61
Quantity:
150
Part Number:
XC3S400-4FTG256C
Manufacturer:
XILINX
Quantity:
20 000
Table 45: Timing for the IOB Three-State Path
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
forth in
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned
to the data Output. When this is true, add the appropriate Output adjustment from
For minimums, use the values reported by the Xilinx timing analyzer.
(2)
(2)
Table 31
R
Time from the active transition at the
OTCLK input of the Three-state
Flip-Flop (TFF) to when the Output pin
enters the high-impedance state
Time from the active transition at TFF’s
OTCLK input to when the Output pin
drives valid data
Time from asserting the Global Three
State (GTS) net to when the Output pin
enters the high-impedance state
Time from asserting TFF’s SR input to
when the Output pin enters a
high-impedance state
Time from asserting TFF’s SR input at
TFF to when the Output pin drives
valid data
and
Table
34.
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
LVCMOS25, 12mA
output drive, Fast slew
rate
LVCMOS25, 12mA
output drive, Fast slew
rate
LVCMOS25, 12mA
output drive, Fast slew
rate
Conditions
Table 47
Table
and are based on the operating conditions set
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
46.
Device
All
All
All
Speed Grade
Max
0.74
0.72
7.71
8.38
1.55
2.24
2.91
-5
Max
0.85
0.82
8.87
9.63
1.78
2.57
3.34
-4
Units
ns
ns
ns
ns
ns
ns
ns
73