XC3S50-4VQG100C Xilinx Inc, XC3S50-4VQG100C Datasheet - Page 11

• Manufacturer Part Number: XC3S50-4VQG100C
• Description: FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S50-4VQG100C

• Package: 100VTQFP
• Family Name: Spartan®-3
• Device Logic Units: 1728
• Device System Gates: 50000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 63
• Ram Bits: 73728
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 192
• Total Ram Bits: 73728
• Number Of I /o: 63
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1504

DS099-2 (v2.5) December 4, 2009
Design Documentation Available
The functionality of the Spartan
described in the following documents. The topics covered in
each guide are listed below.
•
•
© 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS099-2 (v2.5) December 4, 2009
Product Specification
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/support/documentation/
user_guides/ug331.pdf
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UG332: Spartan-3 Generation Configuration User
Guide
http://www.xilinx.com/support/documentation/
user_guides/ug332.pdf
-
-
-
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Configuration Overview
·
·
Detailed Descriptions by Mode
·
·
·
·
ISE iMPACT Programming Examples
®
Configuration Pins and Behavior
Bitstream Sizes
Master Serial Mode using Xilinx Platform Flash
PROM
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
Software Design Tools
R
®
-3 FPGA family is
54
www.xilinx.com
0
Spartan-3 FPGA Family:
Functional Description
Product Specification
For specific hardware examples, please see the Spartan-3
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
•
•
Create a Xilinx MySupport user account and sign up to
receive automatic e-mail notification whenever this data
sheet or the associated user guides are updated.
•
Spartan-3 FPGA Starter Kit Board Page
http://www.xilinx.com/s3starter
UG130: Spartan-3 FPGA Starter Kit User Guide
http://www.xilinx.com/support/documentation/
boards_and_kits/ug130.pdf
Sign Up for Alerts on Xilinx MySupport
http://www.xilinx.com/support/answers/19380.htm
11