XC3S50-4VQG100C Xilinx Inc, XC3S50-4VQG100C Datasheet - Page 151

FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP

XC3S50-4VQG100C

Manufacturer Part Number
XC3S50-4VQG100C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet

Specifications of XC3S50-4VQG100C

Package
100VTQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
63
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
63
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1504

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User I/Os by Bank
Table 98
tributed between the eight I/O banks on the FG320 pack-
age.
Table 98: User I/Os Per Bank in FG320 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
Package Edge
Bottom
Right
Top
Left
indicates how the available user-I/O pins are dis-
R
I/O Bank
0
1
2
3
4
5
6
7
Maximum
I/O
26
26
29
29
27
26
29
29
Maximum
LVDS
Pairs
11
11
14
14
11
11
14
14
www.xilinx.com
I/O
19
19
23
23
13
13
23
23
DUAL
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
Spartan-3 FPGA Family: Pinout Descriptions
DCI
2
2
2
2
2
2
2
2
VREF
3
3
4
4
4
3
4
4
GCLK
2
2
0
0
2
2
0
0
151

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