XC3S500E-4PQ208C Xilinx Inc, XC3S500E-4PQ208C Datasheet - Page 106

• Manufacturer Part Number: XC3S500E-4PQ208C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3S500E-4PQ208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640

Functional Description
106
instruction
JPROG
Load
Figure 68: Boundary-Scan Configuration Flow Diagram
No
Yes
and V
(JTAG port becomes
Load configuration
and V
INIT_B = High?
Load JSTART
(Clock five 1's
Load CFG_IN
Reconfigure?
Synchronous
configuration
data frames
User mode
V
instruction
Power-On
Yes
instruction
TAP reset
sequence
CCO
Yes
mode pins
Yes
available)
on TMS)
Start-Up
correct?
CCINT
memory
Sample
CCAUX
CRC
Clear
Bank 2 > 1V
www.xilinx.com
>1V
> 2V
No
No
No
INIT_B goes Low.
Abort Start-Up
Yes
Set PROG_B Low
after Power-On
PROG_B = Low
DS312-2_59_051706
No
DS312-2 (v3.8) August 26, 2009
Product Specification
R