XC3S700AN-5FGG484C Xilinx Inc, XC3S700AN-5FGG484C Datasheet - Page 122
![FPGA Spartan®-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S700AN-5FGG484C
Manufacturer Part Number
XC3S700AN-5FGG484C
Description
FPGA Spartan®-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-5FGG484C
Package
484FBGA
Family Name
Spartan®-3AN
Device Logic Units
13248
Device System Gates
700000
Maximum Internal Frequency
770 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Total Ram Bits
368640
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-5FGG484C
Manufacturer:
XILINX
Quantity:
748
Company:
Part Number:
XC3S700AN-5FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Revision History
The following table shows the revision history for this document.
DS557 (v4.1) April 1, 2011
Product Specification
02/26/07
08/16/07
09/12/07
09/24/07
12/12/07
06/02/08
11/19/09
12/02/10
04/01/11
Date
Version
2.0.1
1.0
2.0
2.1
3.0
3.1
3.2
4.0
4.1
Initial release.
Updated for Production release of initial device. Noted that family is available in Pb-free packages only.
Minor updates to text.
Update thermal characteristics in
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
non-Pb-free packages may be available for selected devices. Updated thermal characteristics in
Table
Add
unconnected N.C. pins for XC3S700AN FGG484 in
FGG676 in
Renamed package ‘Footprint Area’ to ‘Body Area’ throughout document. Noted in
references to Pb-free package code also apply to the Pb package. Added Pb packages to
Table
for SUSPEND to VCCAUX. Noted that non-Pb-free (Pb) packages are available for selected devices.
Updated
Upgraded
Updated the CLK description in
XC3S50AN and XC3S400AN in the FT(G)256 package and the XC3S1400AN in the FG(G)484
package. In
Mass column, and updated Note 1. In
FGG676 link from PK111_FGG676, and the TQG144 link from PK126_TQG144. Completely replaced
the section
device/package combinations and new figures and tables. Revised U16, U7, and T8 in
Table 80
Package Overview
67. Updated links.
66. Changed Body Area of TQ144/TQG144 packages in
and
Table 79
Notice of
FTG256: 256-Ball Fine-Pitch, Thin Ball Grid Array
Table 82
Table
Table 81
and
65, updated the maximum I/Os for the FG484/FGG484 packages, removed the
Disclaimer.
and
and updated
Figure 22
section. Removed VREF and INPUT designations and diamond symbols on
Figure
www.xilinx.com
Table
23.
for I/O vs. Input pin counts.
Table
Figure
62. In
Table
67.
23.
Table
65, changed the FTG256 link from PK115_FTG256,
Spartan-3AN FPGA Family: Pinout Descriptions
Revision
64, added device/package combinations for the
Table 78
and
with new information on the added
Table
Figure 22
65. Corrected bank designation
and for XC3S1400AN
Introduction
Table
Table 65
78. Added
that
and
122