XC3S700AN-5FGG484C Xilinx Inc, XC3S700AN-5FGG484C Datasheet - Page 46
![FPGA Spartan®-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S700AN-5FGG484C
Manufacturer Part Number
XC3S700AN-5FGG484C
Description
FPGA Spartan®-3AN Family 700K Gates 13248 Cells 770MHz 90nm Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-5FGG484C
Package
484FBGA
Family Name
Spartan®-3AN
Device Logic Units
13248
Device System Gates
700000
Maximum Internal Frequency
770 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Total Ram Bits
368640
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-5FGG484C
Manufacturer:
XILINX
Quantity:
748
Company:
Part Number:
XC3S700AN-5FGG484C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
DS557 (v4.1) April 1, 2011
Product Specification
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
Signal Standard
(IOSTANDARD)
QuietIO
Slow
Fast
2
4
6
2
4
6
2
4
6
Banks 0,2
Bottom
CCO
Top,
17
12
36
13
10
–
–
–
–
–
–
9
–
–
–
–
8
7
–
–
7
5
8
8
1
8
8
8
8
8
8
TQG144
-GND Pair (Cont’d)
Banks 1,3
Right
Package Type
Left,
13
17
13
10
36
33
27
11
13
10
9
9
9
9
9
7
5
8
9
6
8
6
–
–
1
–
–
–
–
–
–
Input Only
Input Only
Banks 0,2
Bottom
Top,
40
31
55
16
17
10
18
22
27
22
27
22
27
27
22
–
–
–
–
–
–
–
–
–
–
7
–
–
8
6
4
FGG400,
FGG484,
FTG256,
FGG676
Banks 1,3
Right
Left,
40
25
18
31
13
55
36
36
16
13
20
17
15
18
10
www.xilinx.com
9
8
5
8
9
9
7
–
–
4
–
–
–
–
–
–
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Switching Outputs per V
Notes:
1.
2.
3.
PPDS_33
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the V
limits for the respective I/O standard.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
Signal Standard
(IOSTANDARD)
Banks 0,2
Bottom
CCO
Top,
8
–
–
6
–
4
3
–
5
–
3
2
TQG144
-GND Pair (Cont’d)
Banks 1,3
Right
Package Type
Left,
–
5
3
6
2
4
6
4
5
3
4
3
Banks 0,2
Bottom
Top,
27
–
–
8
–
5
3
–
9
–
4
3
IL
FGG400,
FGG484,
FTG256,
FGG676
/V
IH
Banks 1,3
voltage
Right
Left,
10
–
4
8
2
4
7
4
9
4
5
3
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