XC5VLX30T-1FF665C Xilinx Inc, XC5VLX30T-1FF665C Datasheet - Page 82
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XC5VLX30T-1FF665C
Manufacturer Part Number
XC5VLX30T-1FF665C
Description
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC5VLX30-1FFG324C.pdf
(91 pages)
Specifications of XC5VLX30T-1FF665C
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
30720
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
1327104
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30T-1FF665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
T
T
PSDCMPLL_0
PHDCMPLL_0
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase
adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package
skew is not included in these measurements.
IFF = Input Flip-Flop.
Symbol
/
No Delay Global Clock and IFF
PLL in Source-Synchronous Mode
Description
(2)
with DCM and
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
0.34
0.83
0.29
0.75
0.35
0.90
0.33
1.07
N/A
N/A
N/A
- 3
Speed Grade
0.40
0.89
0.38
1.12
0.36
0.87
0.32
0.78
0.35
0.92
0.37
1.11
0.29
1.42
- 2
0.40
0.94
0.39
1.17
0.37
0.92
0.32
0.83
0.35
0.96
0.41
1.16
0.33
1.46
- 1
Units
ns
ns
ns
ns
ns
ns
ns
82