XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 308

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
308
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage
1.5V
LVCMOS15_2_slow
LVCMOS15_4_slow
LVCMOS15_6_slow
LVCMOS15_8_slow
LVCMOS15_12_slow
LVCMOS15_16_slow
LVCMOS15_2_fast
LVCMOS15_4_fast
LVCMOS15_6_fast
LVCMOS15_8_fast
LVCMOS15_12_fast
LVCMOS15_16_fast
LVDCI_15 50 Ω
HSTL_I_15
HSTL_I_15_DCI
HSTL_II_15
HSTL_II_15_DCI
HSTL_III_15
HSTL_III_15_DCI
HSTL_IV_15
HSTL_IV_15_DCI
HSLVDCI_15 50 Ω
DIFF_HSTL_I_15
DIFF_HSTL_I_15_DCI
DIFF_HSTL_II_15
DIFF_HSTL_II_15_DCI
IOSTANDARD
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Limit per 20-pin Bank
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
12
12
20
20
20
20
20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
25
25
40
40
40
40
40